Lines Matching refs:Op
601 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, in LowerDYNAMIC_STACKALLOC() argument
610 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, in LowerOperation() argument
612 switch (Op.getOpcode()) { in LowerOperation()
614 Op.getNode()->dump(); in LowerOperation()
618 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
619 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
620 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
621 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG); in LowerOperation()
622 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
623 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
624 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG); in LowerOperation()
625 case ISD::FREM: return LowerFREM(Op, DAG); in LowerOperation()
626 case ISD::FCEIL: return LowerFCEIL(Op, DAG); in LowerOperation()
627 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG); in LowerOperation()
628 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
629 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG); in LowerOperation()
630 case ISD::FROUND: return LowerFROUND(Op, DAG); in LowerOperation()
631 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG); in LowerOperation()
632 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
633 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); in LowerOperation()
634 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); in LowerOperation()
635 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); in LowerOperation()
636 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); in LowerOperation()
638 return Op; in LowerOperation()
776 SDValue Op, in LowerGlobalAddress() argument
780 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op); in LowerGlobalAddress()
804 return DAG.getConstant(Offset, SDLoc(Op), in LowerGlobalAddress()
822 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT); in LowerGlobalAddress()
844 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT); in LowerGlobalAddress()
855 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op, in LowerCONCAT_VECTORS() argument
859 for (const SDUse &U : Op->ops()) in LowerCONCAT_VECTORS()
862 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args); in LowerCONCAT_VECTORS()
865 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, in LowerEXTRACT_SUBVECTOR() argument
869 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); in LowerEXTRACT_SUBVECTOR()
870 EVT VT = Op.getValueType(); in LowerEXTRACT_SUBVECTOR()
871 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start, in LowerEXTRACT_SUBVECTOR()
874 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args); in LowerEXTRACT_SUBVECTOR()
877 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op, in LowerFrameIndex() argument
883 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op); in LowerFrameIndex()
889 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op), in LowerFrameIndex()
890 Op.getValueType()); in LowerFrameIndex()
893 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, in LowerINTRINSIC_WO_CHAIN() argument
895 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); in LowerINTRINSIC_WO_CHAIN()
896 SDLoc DL(Op); in LowerINTRINSIC_WO_CHAIN()
897 EVT VT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN()
900 default: return Op; in LowerINTRINSIC_WO_CHAIN()
903 return LowerIntrinsicIABS(Op, DAG); in LowerINTRINSIC_WO_CHAIN()
905 return LowerIntrinsicLRP(Op, DAG); in LowerINTRINSIC_WO_CHAIN()
910 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN()
914 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN()
920 SDValue Numerator = Op.getOperand(1); in LowerINTRINSIC_WO_CHAIN()
921 SDValue Denominator = Op.getOperand(2); in LowerINTRINSIC_WO_CHAIN()
930 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0, in LowerINTRINSIC_WO_CHAIN()
936 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3), in LowerINTRINSIC_WO_CHAIN()
937 Op.getOperand(4)); in LowerINTRINSIC_WO_CHAIN()
941 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN()
945 Op.getOperand(1), Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
948 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
951 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
954 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
962 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
968 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
972 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
973 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
976 return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
977 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
979 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
980 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
982 return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
983 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
985 return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
986 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
990 Op.getOperand(1), Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
994 Op.getOperand(1), Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
998 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN()
1002 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN()
1005 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1008 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1011 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1014 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1018 Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
1019 Op.getOperand(2), in LowerINTRINSIC_WO_CHAIN()
1020 Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN()
1024 Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
1025 Op.getOperand(2), in LowerINTRINSIC_WO_CHAIN()
1026 Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN()
1030 Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
1031 Op.getOperand(2), in LowerINTRINSIC_WO_CHAIN()
1032 Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN()
1036 Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
1037 Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
1041 Op.getOperand(1), Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()
1044 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1047 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1049 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1051 return DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1056 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op, in LowerIntrinsicIABS() argument
1058 SDLoc DL(Op); in LowerIntrinsicIABS()
1059 EVT VT = Op.getValueType(); in LowerIntrinsicIABS()
1061 Op.getOperand(1)); in LowerIntrinsicIABS()
1063 return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1)); in LowerIntrinsicIABS()
1068 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op, in LowerIntrinsicLRP() argument
1070 SDLoc DL(Op); in LowerIntrinsicLRP()
1071 EVT VT = Op.getValueType(); in LowerIntrinsicLRP()
1075 Op.getOperand(1)); in LowerIntrinsicLRP()
1077 Op.getOperand(3)); in LowerIntrinsicLRP()
1079 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)), in LowerIntrinsicLRP()
1163 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op, in ScalarizeVectorLoad() argument
1165 LoadSDNode *Load = cast<LoadSDNode>(Op); in ScalarizeVectorLoad()
1169 EVT LoadVT = Op.getValueType(); in ScalarizeVectorLoad()
1177 SDLoc SL(Op); in ScalarizeVectorLoad()
1203 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op, in SplitVectorLoad() argument
1205 EVT VT = Op.getValueType(); in SplitVectorLoad()
1210 return ScalarizeVectorLoad(Op, DAG); in SplitVectorLoad()
1212 LoadSDNode *Load = cast<LoadSDNode>(Op); in SplitVectorLoad()
1216 SDLoc SL(Op); in SplitVectorLoad()
1226 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT); in SplitVectorLoad()
1258 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op, in MergeVectorStore() argument
1260 StoreSDNode *Store = cast<StoreSDNode>(Op); in MergeVectorStore()
1271 SDLoc DL(Op); in MergeVectorStore()
1316 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op, in ScalarizeVectorStore() argument
1318 StoreSDNode *Store = cast<StoreSDNode>(Op); in ScalarizeVectorStore()
1323 SDLoc SL(Op); in ScalarizeVectorStore()
1348 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op, in SplitVectorStore() argument
1350 StoreSDNode *Store = cast<StoreSDNode>(Op); in SplitVectorStore()
1357 return ScalarizeVectorStore(Op, DAG); in SplitVectorStore()
1362 SDLoc SL(Op); in SplitVectorStore()
1403 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { in LowerLOAD() argument
1404 SDLoc DL(Op); in LowerLOAD()
1405 LoadSDNode *Load = cast<LoadSDNode>(Op); in LowerLOAD()
1407 EVT VT = Op.getValueType(); in LowerLOAD()
1442 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(), in LowerLOAD()
1445 Op.getOperand(2)); in LowerLOAD()
1483 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { in LowerSTORE() argument
1484 SDLoc DL(Op); in LowerSTORE()
1485 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG); in LowerSTORE()
1490 StoreSDNode *Store = cast<StoreSDNode>(Op); in LowerSTORE()
1495 return SplitVectorStore(Op, DAG); in LowerSTORE()
1546 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const { in LowerDIVREM24() argument
1547 SDLoc DL(Op); in LowerDIVREM24()
1548 EVT VT = Op.getValueType(); in LowerDIVREM24()
1549 SDValue LHS = Op.getOperand(0); in LowerDIVREM24()
1550 SDValue RHS = Op.getOperand(1); in LowerDIVREM24()
1645 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op, in LowerUDIVREM64() argument
1648 assert(Op.getValueType() == MVT::i64); in LowerUDIVREM64()
1650 SDLoc DL(Op); in LowerUDIVREM64()
1651 EVT VT = Op.getValueType(); in LowerUDIVREM64()
1658 SDValue LHS = Op.getOperand(0); in LowerUDIVREM64()
1662 SDValue RHS = Op.getOperand(1); in LowerUDIVREM64()
1720 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op, in LowerUDIVREM() argument
1722 SDLoc DL(Op); in LowerUDIVREM()
1723 EVT VT = Op.getValueType(); in LowerUDIVREM()
1727 LowerUDIVREM64(Op, DAG, Results); in LowerUDIVREM()
1731 SDValue Num = Op.getOperand(0); in LowerUDIVREM()
1732 SDValue Den = Op.getOperand(1); in LowerUDIVREM()
1740 return LowerDIVREM24(Op, DAG, false); in LowerUDIVREM()
1840 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op, in LowerSDIVREM() argument
1842 SDLoc DL(Op); in LowerSDIVREM()
1843 EVT VT = Op.getValueType(); in LowerSDIVREM()
1845 SDValue LHS = Op.getOperand(0); in LowerSDIVREM()
1846 SDValue RHS = Op.getOperand(1); in LowerSDIVREM()
1854 return LowerDIVREM24(Op, DAG, true); in LowerSDIVREM()
1901 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const { in LowerFREM() argument
1902 SDLoc SL(Op); in LowerFREM()
1903 EVT VT = Op.getValueType(); in LowerFREM()
1904 SDValue X = Op.getOperand(0); in LowerFREM()
1905 SDValue Y = Op.getOperand(1); in LowerFREM()
1916 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const { in LowerFCEIL() argument
1917 SDLoc SL(Op); in LowerFCEIL()
1918 SDValue Src = Op.getOperand(0); in LowerFCEIL()
1955 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const { in LowerFTRUNC() argument
1956 SDLoc SL(Op); in LowerFTRUNC()
1957 SDValue Src = Op.getOperand(0); in LowerFTRUNC()
1959 assert(Op.getValueType() == MVT::f64); in LowerFTRUNC()
2005 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const { in LowerFRINT() argument
2006 SDLoc SL(Op); in LowerFRINT()
2007 SDValue Src = Op.getOperand(0); in LowerFRINT()
2009 assert(Op.getValueType() == MVT::f64); in LowerFRINT()
2032 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const { in LowerFNEARBYINT() argument
2036 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0)); in LowerFNEARBYINT()
2040 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const { in LowerFROUND32() argument
2041 SDLoc SL(Op); in LowerFROUND32()
2042 SDValue X = Op.getOperand(0); in LowerFROUND32()
2068 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const { in LowerFROUND64() argument
2069 SDLoc SL(Op); in LowerFROUND64()
2070 SDValue X = Op.getOperand(0); in LowerFROUND64()
2125 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const { in LowerFROUND() argument
2126 EVT VT = Op.getValueType(); in LowerFROUND()
2129 return LowerFROUND32(Op, DAG); in LowerFROUND()
2132 return LowerFROUND64(Op, DAG); in LowerFROUND()
2137 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const { in LowerFFLOOR() argument
2138 SDLoc SL(Op); in LowerFFLOOR()
2139 SDValue Src = Op.getOperand(0); in LowerFFLOOR()
2162 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, in LowerINT_TO_FP64() argument
2164 SDLoc SL(Op); in LowerINT_TO_FP64()
2165 SDValue Src = Op.getOperand(0); in LowerINT_TO_FP64()
2185 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op, in LowerUINT_TO_FP() argument
2187 SDValue S0 = Op.getOperand(0); in LowerUINT_TO_FP()
2191 EVT DestVT = Op.getValueType(); in LowerUINT_TO_FP()
2193 return LowerINT_TO_FP64(Op, DAG, false); in LowerUINT_TO_FP()
2197 SDLoc DL(Op); in LowerUINT_TO_FP()
2212 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op, in LowerSINT_TO_FP() argument
2214 SDValue Src = Op.getOperand(0); in LowerSINT_TO_FP()
2215 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64) in LowerSINT_TO_FP()
2216 return LowerINT_TO_FP64(Op, DAG, true); in LowerSINT_TO_FP()
2221 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, in LowerFP64_TO_INT() argument
2223 SDLoc SL(Op); in LowerFP64_TO_INT()
2225 SDValue Src = Op.getOperand(0); in LowerFP64_TO_INT()
2250 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op, in LowerFP_TO_SINT() argument
2252 SDValue Src = Op.getOperand(0); in LowerFP_TO_SINT()
2254 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64) in LowerFP_TO_SINT()
2255 return LowerFP64_TO_INT(Op, DAG, true); in LowerFP_TO_SINT()
2260 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op, in LowerFP_TO_UINT() argument
2262 SDValue Src = Op.getOperand(0); in LowerFP_TO_UINT()
2264 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64) in LowerFP_TO_UINT()
2265 return LowerFP64_TO_INT(Op, DAG, false); in LowerFP_TO_UINT()
2270 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, in LowerSIGN_EXTEND_INREG() argument
2272 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerSIGN_EXTEND_INREG()
2273 MVT VT = Op.getSimpleValueType(); in LowerSIGN_EXTEND_INREG()
2279 SDValue Src = Op.getOperand(0); in LowerSIGN_EXTEND_INREG()
2280 SDLoc DL(Op); in LowerSIGN_EXTEND_INREG()
2298 static bool isU24(SDValue Op, SelectionDAG &DAG) { in isU24() argument
2300 EVT VT = Op.getValueType(); in isU24()
2301 DAG.computeKnownBits(Op, KnownZero, KnownOne); in isU24()
2306 static bool isI24(SDValue Op, SelectionDAG &DAG) { in isI24() argument
2307 EVT VT = Op.getValueType(); in isI24()
2313 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24; in isI24()
2316 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) { in simplifyI24() argument
2320 EVT VT = Op.getValueType(); in simplifyI24()
2325 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) in simplifyI24()
2618 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const { in isHWTrueValue()
2619 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) { in isHWTrueValue()
2622 return isAllOnesConstant(Op); in isHWTrueValue()
2625 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const { in isHWFalseValue()
2626 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) { in isHWFalseValue()
2629 return isNullConstant(Op); in isHWFalseValue()
2791 const SDValue Op, in computeKnownBitsForTargetNode() argument
2801 unsigned Opc = Op.getOpcode(); in computeKnownBitsForTargetNode()
2808 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { in computeKnownBitsForTargetNode()
2813 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2), in computeKnownBitsForTargetNode()
2830 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2)); in computeKnownBitsForTargetNode()
2846 SDValue Op, in ComputeNumSignBitsForTargetNode() argument
2849 switch (Op.getOpcode()) { in ComputeNumSignBitsForTargetNode()
2851 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2)); in ComputeNumSignBitsForTargetNode()
2856 if (!isNullConstant(Op.getOperand(1))) in ComputeNumSignBitsForTargetNode()
2860 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1); in ComputeNumSignBitsForTargetNode()
2865 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2)); in ComputeNumSignBitsForTargetNode()