Lines Matching refs:SDValue
32 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33 const SDValue &InitPtr,
34 SDValue Chain,
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
46 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
59 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
62 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
63 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
65 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
67 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
68 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
69 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
75 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
79 SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const;
82 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
85 SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const;
88 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
95 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
96 SmallVectorImpl<SDValue> &Results) const;
97 bool isHWTrueValue(SDValue Op) const;
98 bool isHWFalseValue(SDValue Op) const;
123 bool isZExtFree(SDValue Val, EVT VT2) const override;
145 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
148 const SmallVectorImpl<SDValue> &OutVals,
150 SDValue LowerCall(CallLoweringInfo &CLI,
151 SmallVectorImpl<SDValue> &InVals) const override;
153 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
156 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
157 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
159 SmallVectorImpl<SDValue> &Results,
162 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
163 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
164 SDValue CombineFMinMaxLegacy(SDLoc DL,
166 SDValue LHS,
167 SDValue RHS,
168 SDValue True,
169 SDValue False,
170 SDValue CC,
175 SDValue getRsqrtEstimate(SDValue Operand,
179 SDValue getRecipEstimate(SDValue Operand,
191 void computeKnownBitsForTargetNode(const SDValue Op,
197 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
204 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,