31 void AMDGPUInstrInfo::anchor() {}  in anchor()
33 AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &st)  in AMDGPUInstrInfo()  function in AMDGPUInstrInfo
36 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {  in getRegisterInfo()
40 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,  in isCoalescableExtInstr()
47 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,  in isLoadFromStackSlot()
53 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,  in isLoadFromStackSlotPostFE()
59 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,  in hasLoadFromStackSlot()
65 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,  in isStoreFromStackSlot()
70 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,  in isStoreFromStackSlotPostFE()
75 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,  in hasStoreFromStackSlot()
83 AMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,  in convertToThreeAddress()
91 AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,  in storeRegToStackSlot()
101 AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
109 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {  in expandPostRAPseudo()
155 MachineInstr *AMDGPUInstrInfo::foldMemoryOperandImpl(  in foldMemoryOperandImpl()
161 MachineInstr *AMDGPUInstrInfo::foldMemoryOperandImpl(  in foldMemoryOperandImpl()
168 AMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,  in unfoldMemoryOperand()
177 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,  in unfoldMemoryOperand()
184 AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,  in getOpcodeAfterMemoryUnfold()
191 bool AMDGPUInstrInfo::enableClusterLoads() const {  in enableClusterLoads()
205 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,  in shouldScheduleLoadsNear()
218 AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)  in ReverseBranchCondition()
223 void AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB,  in insertNoop()
228 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {  in isPredicated()
233 bool AMDGPUInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,  in SubsumesPredicate()
239 bool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI,  in DefinesPredicate()
245 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {  in isPredicable()
251 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {  in isSafeToMoveRegClassDefs()
256 bool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const {  in isRegisterStore()
260 bool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const {  in isRegisterLoad()
264 int AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {  in getIndirectIndexBegin()
299 int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {  in getIndirectIndexEnd()
317 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {  in getMaskedMIMGOp()
352 int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const {  in pseudoToMCOpcode()
369 AMDGPUInstrInfo::getSerializableTargetIndices() const {  in getSerializableTargetIndices()