Lines Matching refs:isReg
112 if (isReg()) in addRegOrImmOperands()
178 bool isReg() const override { in isReg() function in __anon2fa8e53e0111::AMDGPUOperand
187 assert(isReg()); in setModifiers()
201 return isReg() || isImm(); in isRegOrImm()
209 return isInlineImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID)); in isSCSrc32()
213 return isImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID)); in isSSrc32()
218 (isReg() && isRegClass(AMDGPU::SReg_64RegClassID)); in isSSrc64()
222 return (isReg() && isRegClass(AMDGPU::SReg_64RegClassID)) || isInlineImm(); in isSCSrc64()
226 return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID)); in isVCSrc32()
230 return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID)); in isVCSrc64()
234 return isImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID)); in isVSrc32()
238 return isImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID)); in isVSrc64()
1430 if (Op.isReg()) { in cvtDSOffset01()
1458 if (Op.isReg()) { in cvtDS()
1622 if (Op.isReg()) { in cvtFlat()
1698 if (Op.isReg()) { in cvtMubuf()
1807 if (DstOp.isReg() && DstOp.isRegClass(AMDGPU::SGPR_64RegClassID)) in isVOP3()
1842 if (Op.isReg()) in parseVOP3OptionalOps()