Lines Matching refs:MVT
36 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
38 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
39 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
40 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
41 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
46 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in R600TargetLowering()
47 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in R600TargetLowering()
48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); in R600TargetLowering()
49 setCondCodeAction(ISD::SETLE, MVT::f32, Expand); in R600TargetLowering()
50 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); in R600TargetLowering()
51 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in R600TargetLowering()
52 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in R600TargetLowering()
53 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in R600TargetLowering()
54 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in R600TargetLowering()
55 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in R600TargetLowering()
56 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
57 setCondCodeAction(ISD::SETULE, MVT::f32, Expand); in R600TargetLowering()
59 setCondCodeAction(ISD::SETLE, MVT::i32, Expand); in R600TargetLowering()
60 setCondCodeAction(ISD::SETLT, MVT::i32, Expand); in R600TargetLowering()
61 setCondCodeAction(ISD::SETULE, MVT::i32, Expand); in R600TargetLowering()
62 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
64 setOperationAction(ISD::FCOS, MVT::f32, Custom); in R600TargetLowering()
65 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
67 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); in R600TargetLowering()
68 setOperationAction(ISD::SETCC, MVT::v2i32, Expand); in R600TargetLowering()
70 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in R600TargetLowering()
71 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in R600TargetLowering()
72 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in R600TargetLowering()
74 setOperationAction(ISD::FSUB, MVT::f32, Expand); in R600TargetLowering()
76 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in R600TargetLowering()
77 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in R600TargetLowering()
78 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom); in R600TargetLowering()
80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
83 setOperationAction(ISD::SETCC, MVT::i32, Expand); in R600TargetLowering()
84 setOperationAction(ISD::SETCC, MVT::f32, Expand); in R600TargetLowering()
85 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom); in R600TargetLowering()
86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in R600TargetLowering()
87 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in R600TargetLowering()
89 setOperationAction(ISD::SELECT, MVT::i32, Expand); in R600TargetLowering()
90 setOperationAction(ISD::SELECT, MVT::f32, Expand); in R600TargetLowering()
91 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); in R600TargetLowering()
92 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); in R600TargetLowering()
97 setOperationAction(ISD::UADDO, MVT::i32, Custom); in R600TargetLowering()
100 setOperationAction(ISD::USUBO, MVT::i32, Custom); in R600TargetLowering()
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); in R600TargetLowering()
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); in R600TargetLowering()
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in R600TargetLowering()
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); in R600TargetLowering()
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand); in R600TargetLowering()
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand); in R600TargetLowering()
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); in R600TargetLowering()
127 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
128 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); in R600TargetLowering()
129 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
133 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
142 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
143 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
147 setOperationAction(ISD::STORE, MVT::i8, Custom); in R600TargetLowering()
148 setOperationAction(ISD::STORE, MVT::i32, Custom); in R600TargetLowering()
149 setOperationAction(ISD::STORE, MVT::v2i32, Custom); in R600TargetLowering()
150 setOperationAction(ISD::STORE, MVT::v4i32, Custom); in R600TargetLowering()
151 setTruncStoreAction(MVT::i32, MVT::i8, Custom); in R600TargetLowering()
152 setTruncStoreAction(MVT::i32, MVT::i16, Custom); in R600TargetLowering()
154 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
155 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
156 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in R600TargetLowering()
158 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
159 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
160 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
161 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
163 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
164 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
165 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
166 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
176 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in R600TargetLowering()
177 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in R600TargetLowering()
178 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); in R600TargetLowering()
180 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in R600TargetLowering()
182 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; in R600TargetLowering()
183 for (MVT VT : ScalarIntVTs) { in R600TargetLowering()
631 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
632 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
633 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
634 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
670 MVT::v4f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32)); in LowerOperation()
673 DL, MVT::f32, SDValue(interp, 0)); in LowerOperation()
682 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32); in LowerOperation()
684 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32); in LowerOperation()
688 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32), in LowerOperation()
692 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32), in LowerOperation()
705 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32), in LowerOperation()
709 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32), in LowerOperation()
711 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32, in LowerOperation()
765 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
767 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
768 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
769 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
770 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
774 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
775 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
776 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
777 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
785 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
789 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
790 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
791 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
792 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
793 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
794 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
795 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
796 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
797 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
798 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
799 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
800 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
801 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
802 DAG.getConstant(3, DL, MVT::i32)), in LowerOperation()
803 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
804 DAG.getConstant(3, DL, MVT::i32)) in LowerOperation()
806 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
874 if (N->getValueType(0) == MVT::i1) { in ReplaceNodeResults()
964 DAG.getConstantFP(0.15915494309, DL, MVT::f32)), in LowerTrig()
965 DAG.getConstantFP(0.5, DL, MVT::f32))); in LowerTrig()
979 DAG.getConstantFP(-0.5, DL, MVT::f32))); in LowerTrig()
984 DAG.getConstantFP(3.14159265359, DL, MVT::f32)); in LowerTrig()
1072 DAG.getValueType(MVT::i1)); in LowerUADDSUBO()
1084 MVT::i1, in LowerFPTOUINT()
1085 Op, DAG.getConstantFP(0.0f, DL, MVT::f32), in LowerFPTOUINT()
1101 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR in LowerImplicitParameter()
1127 if (VT == MVT::f32) { in LowerSELECT_CC()
1151 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32); in LowerSELECT_CC()
1167 (CompareVT == VT || VT == MVT::i32)) { in LowerSELECT_CC()
1218 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32); in LowerSELECT_CC()
1237 if (CompareVT == MVT::f32) { in LowerSELECT_CC()
1240 } else if (CompareVT == MVT::i32) { in LowerSELECT_CC()
1282 DAG.getConstant(SRLPad, DL, MVT::i32)); in stackPtrToRegIndex()
1329 assert(VT.bitsLE(MVT::i32)); in LowerSTORE()
1332 if (MemVT == MVT::i8) { in LowerSTORE()
1333 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32); in LowerSTORE()
1335 assert(MemVT == MVT::i16); in LowerSTORE()
1336 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32); in LowerSTORE()
1339 DAG.getConstant(2, DL, MVT::i32)); in LowerSTORE()
1351 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1352 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1355 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src); in LowerSTORE()
1361 Value.getValueType().bitsGE(MVT::i32)) { in LowerSTORE()
1365 Ptr, DAG.getConstant(2, DL, MVT::i32))); in LowerSTORE()
1406 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, in LowerSTORE()
1407 DAG.getConstant(PtrIncr, DL, MVT::i32)); in LowerSTORE()
1409 Value, DAG.getConstant(i, DL, MVT::i32)); in LowerSTORE()
1411 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, in LowerSTORE()
1413 DAG.getTargetConstant(Channel, DL, MVT::i32)); in LowerSTORE()
1415 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores); in LowerSTORE()
1417 if (ValueVT == MVT::i8) { in LowerSTORE()
1418 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value); in LowerSTORE()
1420 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr, in LowerSTORE()
1421 DAG.getTargetConstant(0, DL, MVT::i32)); // Channel in LowerSTORE()
1488 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1489 DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1492 DAG.getTargetConstant(0, DL, MVT::i32), in LowerLOAD()
1520 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32)); in LowerLOAD()
1521 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in LowerLOAD()
1523 EVT NewVT = MVT::v4i32; in LowerLOAD()
1533 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1534 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1535 DAG.getConstant(4, DL, MVT::i32)), in LowerLOAD()
1537 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32) in LowerLOAD()
1542 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1543 DAG.getConstant(0, DL, MVT::i32)); in LowerLOAD()
1562 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8)); in LowerLOAD()
1599 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, in LowerLOAD()
1600 DAG.getConstant(PtrIncr, DL, MVT::i32)); in LowerLOAD()
1603 DAG.getTargetConstant(Channel, DL, MVT::i32), in LowerLOAD()
1614 DAG.getTargetConstant(0, DL, MVT::i32), // Channel in LowerLOAD()
1703 DAG.getConstant(Offset, DL, MVT::i32), in LowerFormalArguments()
1704 DAG.getUNDEF(MVT::i32), in LowerFormalArguments()
1718 return MVT::i32; in getSetCCResultType()
1743 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1746 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1815 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1823 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1843 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1862 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS in PerformDAGCombine()
1863 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True in PerformDAGCombine()
1873 DAG.getConstant(-1, dl, MVT::i32), // True in PerformDAGCombine()
1874 DAG.getConstant(0, dl, MVT::i32), // False in PerformDAGCombine()
2068 Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2074 Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2127 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32); in FoldOperand()
2170 Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2172 Src = DAG.getRegister(ImmReg, MVT::i32); in FoldOperand()
2255 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, DL, MVT::i32); in PostISelFolding()