Lines Matching refs:TRI
68 const SIRegisterInfo *TRI = &TII->getRegisterInfo(); in emitPrologue() local
78 unsigned PreloadedScratchWaveOffsetReg = TRI->getPreloadedValue( in emitPrologue()
83 PreloadedPrivateBufferReg = TRI->getPreloadedValue( in emitPrologue()
118 if (ScratchRsrcReg == TRI->reservedPrivateSegmentBufferReg(MF)) { in emitPrologue()
137 if (ScratchWaveOffsetReg == TRI->reservedPrivateSegmentWaveByteOffsetReg(MF)) { in emitPrologue()
147 !TRI->isSubRegisterEq(ScratchRsrcReg, Reg)); in emitPrologue()
158 assert(!TRI->isSubRegister(ScratchRsrcReg, ScratchWaveOffsetReg)); in emitPrologue()
174 !TRI->isSubRegisterEq(PreloadedPrivateBufferReg, ScratchRsrcReg) && in emitPrologue()
175 !TRI->isSubRegisterEq(PreloadedPrivateBufferReg, ScratchWaveOffsetReg)); in emitPrologue()
177 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitPrologue()
178 unsigned Rsrc23 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2_sub3); in emitPrologue()
180 unsigned Lo = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub0_sub1); in emitPrologue()
181 unsigned Hi = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub2_sub3); in emitPrologue()
190 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitPrologue()
191 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitPrologue()
192 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitPrologue()
193 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitPrologue()