Lines Matching refs:MVT
42 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
43 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
45 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); in SITargetLowering()
46 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); in SITargetLowering()
48 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
49 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
51 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass); in SITargetLowering()
52 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
53 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass); in SITargetLowering()
55 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass); in SITargetLowering()
56 addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass); in SITargetLowering()
58 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass); in SITargetLowering()
59 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass); in SITargetLowering()
61 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass); in SITargetLowering()
62 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass); in SITargetLowering()
64 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass); in SITargetLowering()
65 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass); in SITargetLowering()
69 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); in SITargetLowering()
70 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand); in SITargetLowering()
71 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); in SITargetLowering()
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); in SITargetLowering()
74 setOperationAction(ISD::ADD, MVT::i32, Legal); in SITargetLowering()
75 setOperationAction(ISD::ADDC, MVT::i32, Legal); in SITargetLowering()
76 setOperationAction(ISD::ADDE, MVT::i32, Legal); in SITargetLowering()
77 setOperationAction(ISD::SUBC, MVT::i32, Legal); in SITargetLowering()
78 setOperationAction(ISD::SUBE, MVT::i32, Legal); in SITargetLowering()
80 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
81 setOperationAction(ISD::FCOS, MVT::f32, Custom); in SITargetLowering()
83 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SITargetLowering()
84 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SITargetLowering()
87 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in SITargetLowering()
88 setOperationAction(ISD::LOAD, MVT::v8i32, Custom); in SITargetLowering()
89 setOperationAction(ISD::LOAD, MVT::v16i32, Custom); in SITargetLowering()
91 setOperationAction(ISD::STORE, MVT::v8i32, Custom); in SITargetLowering()
92 setOperationAction(ISD::STORE, MVT::v16i32, Custom); in SITargetLowering()
94 setOperationAction(ISD::STORE, MVT::i1, Custom); in SITargetLowering()
95 setOperationAction(ISD::STORE, MVT::v4i32, Custom); in SITargetLowering()
97 setOperationAction(ISD::SELECT, MVT::i64, Custom); in SITargetLowering()
98 setOperationAction(ISD::SELECT, MVT::f64, Promote); in SITargetLowering()
99 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64); in SITargetLowering()
101 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in SITargetLowering()
102 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in SITargetLowering()
103 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in SITargetLowering()
104 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in SITargetLowering()
106 setOperationAction(ISD::SETCC, MVT::v2i1, Expand); in SITargetLowering()
107 setOperationAction(ISD::SETCC, MVT::v4i1, Expand); in SITargetLowering()
109 setOperationAction(ISD::BSWAP, MVT::i32, Legal); in SITargetLowering()
110 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in SITargetLowering()
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal); in SITargetLowering()
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom); in SITargetLowering()
114 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom); in SITargetLowering()
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal); in SITargetLowering()
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); in SITargetLowering()
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom); in SITargetLowering()
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); in SITargetLowering()
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); in SITargetLowering()
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom); in SITargetLowering()
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in SITargetLowering()
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom); in SITargetLowering()
127 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in SITargetLowering()
128 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom); in SITargetLowering()
129 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom); in SITargetLowering()
130 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom); in SITargetLowering()
132 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in SITargetLowering()
133 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in SITargetLowering()
135 for (MVT VT : MVT::integer_valuetypes()) { in SITargetLowering()
136 if (VT == MVT::i64) in SITargetLowering()
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
141 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
142 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
144 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
145 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
147 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
149 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
150 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
151 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
152 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
155 for (MVT VT : MVT::integer_vector_valuetypes()) { in SITargetLowering()
156 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i16, Expand); in SITargetLowering()
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand); in SITargetLowering()
160 for (MVT VT : MVT::fp_valuetypes()) in SITargetLowering()
161 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SITargetLowering()
163 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand); in SITargetLowering()
164 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand); in SITargetLowering()
166 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in SITargetLowering()
167 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand); in SITargetLowering()
168 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand); in SITargetLowering()
169 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand); in SITargetLowering()
172 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand); in SITargetLowering()
174 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); in SITargetLowering()
175 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand); in SITargetLowering()
177 setOperationAction(ISD::LOAD, MVT::i1, Custom); in SITargetLowering()
179 setOperationAction(ISD::LOAD, MVT::v2i64, Promote); in SITargetLowering()
180 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32); in SITargetLowering()
182 setOperationAction(ISD::STORE, MVT::v2i64, Promote); in SITargetLowering()
183 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32); in SITargetLowering()
185 setOperationAction(ISD::ConstantPool, MVT::v2i64, Expand); in SITargetLowering()
187 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in SITargetLowering()
188 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in SITargetLowering()
189 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in SITargetLowering()
192 setOperationAction(ISD::UDIV, MVT::i64, Expand); in SITargetLowering()
193 setOperationAction(ISD::UREM, MVT::i64, Expand); in SITargetLowering()
195 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); in SITargetLowering()
196 setOperationAction(ISD::SELECT, MVT::i1, Promote); in SITargetLowering()
198 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand); in SITargetLowering()
201 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in SITargetLowering()
205 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) { in SITargetLowering()
230 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) { in SITargetLowering()
232 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32); in SITargetLowering()
235 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
238 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
241 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32); in SITargetLowering()
245 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in SITargetLowering()
246 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in SITargetLowering()
247 setOperationAction(ISD::FRINT, MVT::f64, Legal); in SITargetLowering()
250 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in SITargetLowering()
251 setOperationAction(ISD::FDIV, MVT::f32, Custom); in SITargetLowering()
252 setOperationAction(ISD::FDIV, MVT::f64, Custom); in SITargetLowering()
443 if (!VT.isSimple() || VT == MVT::Other) in allowsMisalignedMemoryAccesses()
464 if (VT.bitsLT(MVT::i32)) in allowsMisalignedMemoryAccesses()
473 return VT.bitsGT(MVT::i32) && Align % 4 == 0; in allowsMisalignedMemoryAccesses()
487 return MVT::v4i32; in getOptimalMemOpType()
490 return MVT::v2i32; in getOptimalMemOpType()
493 return MVT::Other; in getOptimalMemOpType()
524 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16)) in getPreferredVectorAction()
549 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS); in LowerParameter()
686 MVT VT = VA.getLocVT(); in LowerFormalArguments()
707 DAG.getValueType(MVT::i16)); in LowerFormalArguments()
718 if (VT == MVT::i64) { in LowerFormalArguments()
872 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerFormalArguments()
901 return MVT::i1; in getSetCCResultType()
903 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements()); in getSetCCResultType()
906 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const { in getScalarShiftAmountTy()
907 return MVT::i32; in getScalarShiftAmountTy()
932 case MVT::f32: in isFMAFasterThanFMulAndFAdd()
938 case MVT::f64: in isFMAFasterThanFMulAndFAdd()
1016 SDValue TFI = DAG.getTargetFrameIndex(FrameIndex, MVT::i32); in LowerFrameIndex()
1020 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI, in LowerFrameIndex()
1111 MVT PtrVT = getPointerTy(DAG.getDataLayout(), GSD->getAddressSpace()); in LowerGlobalAddress()
1113 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32); in LowerGlobalAddress()
1128 return DAG.getCopyToReg(Chain, DL, DAG.getRegister(AMDGPU::M0, MVT::i32), in copyToM0()
1136 MVT VT, in lowerImplicitZextParam()
1139 SDValue Param = LowerParameter(DAG, MVT::i32, MVT::i32, SL, in lowerImplicitZextParam()
1142 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param, in lowerImplicitZextParam()
1183 return lowerImplicitZextParam(DAG, Op, MVT::i16, in LowerINTRINSIC_WO_CHAIN()
1186 return lowerImplicitZextParam(DAG, Op, MVT::i16, in LowerINTRINSIC_WO_CHAIN()
1189 return lowerImplicitZextParam(DAG, Op, MVT::i16, in LowerINTRINSIC_WO_CHAIN()
1193 return lowerImplicitZextParam(DAG, Op, MVT::i8, in LowerINTRINSIC_WO_CHAIN()
1247 return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32, in LowerINTRINSIC_WO_CHAIN()
1248 DAG.getConstant(2, DL, MVT::i32), // P0 in LowerINTRINSIC_WO_CHAIN()
1253 return DAG.getUNDEF(MVT::i32); in LowerINTRINSIC_WO_CHAIN()
1257 SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ, in LowerINTRINSIC_WO_CHAIN()
1258 DAG.getConstant(0, DL, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
1259 SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ, in LowerINTRINSIC_WO_CHAIN()
1260 DAG.getConstant(1, DL, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
1264 DAG.getVTList(MVT::f32, MVT::Glue), in LowerINTRINSIC_WO_CHAIN()
1267 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, P1, J, in LowerINTRINSIC_WO_CHAIN()
1273 return DAG.getNode(AMDGPUISD::INTERP_P1, DL, MVT::f32, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
1279 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
1299 return DAG.getNode(AMDGPUISD::SENDMSG, DL, MVT::Other, Chain, in LowerINTRINSIC_VOID()
1339 assert(Op.getValueType().getVectorElementType() == MVT::i32 && in LowerLOAD()
1382 if (Op.getValueType() != MVT::i64) in LowerSELECT()
1388 SDValue Zero = DAG.getConstant(0, DL, MVT::i32); in LowerSELECT()
1389 SDValue One = DAG.getConstant(1, DL, MVT::i32); in LowerSELECT()
1391 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1)); in LowerSELECT()
1392 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2)); in LowerSELECT()
1394 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero); in LowerSELECT()
1395 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero); in LowerSELECT()
1397 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1); in LowerSELECT()
1399 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One); in LowerSELECT()
1400 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One); in LowerSELECT()
1402 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1); in LowerSELECT()
1404 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi); in LowerSELECT()
1405 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res); in LowerSELECT()
1418 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) && in LowerFastFDIV()
1463 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS); in LowerFDIV32()
1466 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32); in LowerFDIV32()
1469 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32); in LowerFDIV32()
1471 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32); in LowerFDIV32()
1474 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32); in LowerFDIV32()
1478 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One); in LowerFDIV32()
1482 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3); in LowerFDIV32()
1484 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1); in LowerFDIV32()
1486 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0); in LowerFDIV32()
1488 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul); in LowerFDIV32()
1499 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64); in LowerFDIV64()
1501 SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1); in LowerFDIV64()
1505 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0); in LowerFDIV64()
1507 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64()
1509 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64()
1511 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64()
1513 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One); in LowerFDIV64()
1517 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1); in LowerFDIV64()
1518 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64()
1520 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64, in LowerFDIV64()
1529 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32); in LowerFDIV64()
1532 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X); in LowerFDIV64()
1533 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y); in LowerFDIV64()
1534 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0); in LowerFDIV64()
1535 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64()
1537 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi); in LowerFDIV64()
1538 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi); in LowerFDIV64()
1541 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi); in LowerFDIV64()
1543 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi); in LowerFDIV64()
1545 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ); in LowerFDIV64()
1546 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ); in LowerFDIV64()
1547 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen); in LowerFDIV64()
1552 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64, in LowerFDIV64()
1555 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X); in LowerFDIV64()
1561 if (VT == MVT::f32) in LowerFDIV()
1564 if (VT == MVT::f64) in LowerFDIV()
1589 if (VT == MVT::i1) in LowerSTORE()
1591 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32), in LowerSTORE()
1592 Store->getBasePtr(), MVT::i1, Store->getMemOperand()); in LowerSTORE()
1625 if (ScalarVT != MVT::f32) in performUCharToFloatCombine()
1638 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) { in performUCharToFloatCombine()
1652 SrcVT.getVectorElementType() != MVT::i8) { in performUCharToFloatCombine()
1669 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts); in performUCharToFloatCombine()
1708 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt); in performUCharToFloatCombine()
1795 SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32); in performSHLPtrCombine()
1845 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1, in performAndCombine()
1846 X, DAG.getConstant(Mask, DL, MVT::i32)); in performAndCombine()
1877 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1, in performOrCombine()
1878 Src, DAG.getConstant(NewMask, DL, MVT::i32)); in performOrCombine()
1892 return DAG.getConstant(0, SDLoc(N), MVT::i1); in performClassCombine()
1962 if (VT != MVT::f32 && VT != MVT::f64) in performSetCCCombine()
1976 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0), in performSetCCCombine()
1977 DAG.getConstant(Mask, SL, MVT::i32)); in performSetCCCombine()
2001 N->getValueType(0) != MVT::f64 && in PerformDAGCombine()
2036 if (VT != MVT::f32) in PerformDAGCombine()
2054 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32); in PerformDAGCombine()
2063 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32); in PerformDAGCombine()
2081 if (VT == MVT::f32 && in PerformDAGCombine()
2090 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32); in PerformDAGCombine()
2102 const SDValue NegTwo = DAG.getConstantFP(-2.0, DL, MVT::f32); in PerformDAGCombine()
2180 if (Node->getValueType(0) == MVT::f32) in analyzeImmediate()
2245 Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32)); in adjustWritemask()
2253 MVT::i32); in adjustWritemask()
2268 SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32); in adjustWritemask()
2375 SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32); in buildSMovImm32()
2376 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0); in buildSMovImm32()
2389 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32), in wrapAddr64Rsrc()
2391 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32), in wrapAddr64Rsrc()
2393 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32) in wrapAddr64Rsrc()
2397 MVT::v2i32, Ops0), 0); in wrapAddr64Rsrc()
2401 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32), in wrapAddr64Rsrc()
2403 DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32), in wrapAddr64Rsrc()
2405 DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32) in wrapAddr64Rsrc()
2408 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1); in wrapAddr64Rsrc()
2420 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr); in buildRSRC()
2421 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr); in buildRSRC()
2423 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi, in buildRSRC()
2424 DAG.getConstant(RsrcDword1, DL, MVT::i32)), in buildRSRC()
2433 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32), in buildRSRC()
2435 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32), in buildRSRC()
2437 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32), in buildRSRC()
2439 DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32), in buildRSRC()
2441 DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32) in buildRSRC()
2444 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops); in buildRSRC()
2463 MVT VT) const { in getRegForInlineAsmConstraint()