39 SITargetLowering::SITargetLowering(TargetMachine &TM,  in SITargetLowering()  function in SITargetLowering
295 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,  in isShuffleMaskLegal()
302 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {  in isLegalFlatAddressingMode()
308 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {  in isLegalMUBUFAddressingMode()
343 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,  in isLegalAddressingMode()
434 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,  in allowsMisalignedMemoryAccesses()
476 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,  in getOptimalMemOpType()
502 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,  in isNoopAddrSpaceCast()
508 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {  in isMemOpUniform()
523 SITargetLowering::getPreferredVectorAction(EVT VT) const {  in getPreferredVectorAction()
530 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,  in shouldConvertConstantLoadToIntImm()
537 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,  in LowerParameter()
572 SDValue SITargetLowering::LowerFormalArguments(  in LowerFormalArguments()
875 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(  in EmitInstrWithCustomInserter()
887 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {  in enableAggressiveFMAFusion()
898 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,  in getSetCCResultType()
906 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {  in getScalarShiftAmountTy()
925 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {  in isFMAFasterThanFMulAndFAdd()
951 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {  in LowerOperation()
997 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {  in LowerFrameIndex()
1026 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,  in LowerBRCOND()
1101 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,  in LowerGlobalAddress()
1117 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL,  in copyToM0()
1134 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,  in lowerImplicitZextParam()
1146 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,  in LowerINTRINSIC_WO_CHAIN()
1288 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,  in LowerINTRINSIC_VOID()
1334 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {  in LowerLOAD()
1372 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,  in LowerSampleIntrinsic()
1381 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {  in LowerSELECT()
1410 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {  in LowerFastFDIV()
1449 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV32()
1491 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV64()
1558 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV()
1570 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {  in LowerSTORE()
1597 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {  in LowerTrig()
1621 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,  in performUCharToFloatCombine()
1767 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,  in performSHLPtrCombine()
1800 SDValue SITargetLowering::performAndCombine(SDNode *N,  in performAndCombine()
1854 SDValue SITargetLowering::performOrCombine(SDNode *N,  in performOrCombine()
1884 SDValue SITargetLowering::performClassCombine(SDNode *N,  in performClassCombine()
1917 SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,  in performMin3Max3Combine()
1953 SDValue SITargetLowering::performSetCCCombine(SDNode *N,  in performSetCCCombine()
1984 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
2163 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {  in analyzeImmediate()
2201 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,  in adjustWritemask()
2290 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,  in legalizeTargetIndependentNode()
2310 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,  in PostISelFolding()
2328 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,  in AdjustInstrPostInstrSelection()
2379 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,  in wrapAddr64Rsrc()
2415 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,  in buildRSRC()
2447 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,  in CreateLiveInRegister()
2461 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,  in getRegForInlineAsmConstraint()
2520 SITargetLowering::ConstraintType
2521 SITargetLowering::getConstraintType(StringRef Constraint) const {  in getConstraintType()