Lines Matching refs:BuildMI
368 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg) in copyPhysReg()
375 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC) in copyPhysReg()
380 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32)) in copyPhysReg()
389 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) in copyPhysReg()
411 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) in copyPhysReg()
460 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL, in copyPhysReg()
565 BuildMI(MBB, MI, DL, get(Opcode)) in storeRegToStackSlot()
577 BuildMI(MBB, MI, DL, get(AMDGPU::KILL)) in storeRegToStackSlot()
587 BuildMI(MBB, MI, DL, get(Opcode)) in storeRegToStackSlot()
651 BuildMI(MBB, MI, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
662 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg); in loadRegFromStackSlot()
670 BuildMI(MBB, MI, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
723 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0) in calculateLDSSpillAddress()
726 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1) in calculateLDSSpillAddress()
731 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1) in calculateLDSSpillAddress()
735 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg) in calculateLDSSpillAddress()
739 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg) in calculateLDSSpillAddress()
744 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg) in calculateLDSSpillAddress()
749 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64), in calculateLDSSpillAddress()
754 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64), in calculateLDSSpillAddress()
760 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32), in calculateLDSSpillAddress()
769 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg) in calculateLDSSpillAddress()
785 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP)) in insertWaitStates()
811 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
814 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
819 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
822 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
838 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo) in expandPostRAPseudo()
842 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi) in expandPostRAPseudo()
861 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg)); in expandPostRAPseudo()
865 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo) in expandPostRAPseudo()
868 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi) in expandPostRAPseudo()
1018 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32), in buildMovInstr()
1271 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32)) in convertToThreeAddress()
1701 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg) in legalizeOpWithMove()
1718 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) in buildExtractSubReg()
1729 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg) in buildExtractSubReg()
1732 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) in buildExtractSubReg()
2020 BuildMI(*InsertBB, Insert, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg) in legalizeOperands()
2048 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg) in legalizeOperands()
2069 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0) in legalizeOperands()
2106 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64), in legalizeOperands()
2111 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), in legalizeOperands()
2116 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), in legalizeOperands()
2121 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc) in legalizeOperands()
2139 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo) in legalizeOperands()
2144 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi) in legalizeOperands()
2149 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr) in legalizeOperands()
2174 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode)) in legalizeOperands()
2200 Addr64 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode)) in legalizeOperands()
2217 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr) in legalizeOperands()
2261 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo) in splitSMRD()
2270 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR) in splitSMRD()
2272 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi) in splitSMRD()
2277 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi) in splitSMRD()
2285 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo) in splitSMRD()
2289 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR) in splitSMRD()
2292 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi) in splitSMRD()
2330 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDst) in splitSMRD()
2366 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), in moveSMRDToVALU()
2370 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), in moveSMRDToVALU()
2384 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1) in moveSMRDToVALU()
2386 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2) in moveSMRDToVALU()
2388 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3) in moveSMRDToVALU()
2390 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc) in moveSMRDToVALU()
2408 BuildMI(*MBB, MI, MI->getDebugLoc(), NewInstDesc, NewDstReg) in moveSMRDToVALU()
2635 BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg) in lowerScalarAbs()
2639 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg) in lowerScalarAbs()
2675 BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitUnaryOp()
2682 BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitUnaryOp()
2686 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitUnaryOp()
2737 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp()
2747 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp()
2752 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitBinaryOp()
2795 BuildMI(MBB, MII, DL, InstDesc, MidReg) in splitScalar64BitBCNT()
2799 BuildMI(MBB, MII, DL, InstDesc, ResultReg) in splitScalar64BitBCNT()
2835 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo) in splitScalar64BitBFE()
2840 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi) in splitScalar64BitBFE()
2844 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
2859 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg) in splitScalar64BitBFE()
2863 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
2989 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1)) in buildIndirectWrite()
3007 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC_V1)) in buildIndirectRead()