1806   const MCInstrDesc &InstDesc = get(MI->getOpcode());  in isOperandLegal()  local
1807   const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];  in isOperandLegal()
2660   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitUnaryOp()  local
2675   BuildMI(MBB, MII, DL, InstDesc, DestSub0)  in splitScalar64BitUnaryOp()
2682   BuildMI(MBB, MII, DL, InstDesc, DestSub1)  in splitScalar64BitUnaryOp()
2715   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitBinaryOp()  local
2737   MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)  in splitScalar64BitBinaryOp()
2747   MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)  in splitScalar64BitBinaryOp()
2780   const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);  in splitScalar64BitBCNT()  local
2795   BuildMI(MBB, MII, DL, InstDesc, MidReg)  in splitScalar64BitBCNT()
2799   BuildMI(MBB, MII, DL, InstDesc, ResultReg)  in splitScalar64BitBCNT()