30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)  in SIInstrInfo()  function in SIInstrInfo
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,  in isReallyTriviallyReMaterializable()
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,  in areLoadsFromSameBasePtr()
204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,  in getMemOpBaseRegImmOfs()
291 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,  in shouldClusterLoads()
312 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
473 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {  in commuteOpcode()
493 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {  in getMovOpcode()
539 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,  in storeRegToStackSlot()
629 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
678 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,  in calculateLDSSpillAddress()
776 void SIInstrInfo::insertWaitStates(MachineBasicBlock::iterator MI,  in insertWaitStates()
790 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {  in expandPostRAPseudo()
888 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI,  in commuteInstructionImpl()
974 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,  in findCommutedOpIndices()
1014 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,  in buildMovInstr()
1022 bool SIInstrInfo::isMov(unsigned Opcode) const {  in isMov()
1047 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,  in FoldImmediate()
1180 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,  in checkInstOffsetsDoNotOverlap()
1200 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,  in areMemAccessesTriviallyDisjoint()
1251 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,  in convertToThreeAddress()
1283 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {  in isInlineConstant()
1322 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,  in isInlineConstant()
1338 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,  in isLiteralConstant()
1358 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,  in isImmOperandLegal()
1377 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {  in hasVALU32BitEncoding()
1385 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {  in hasModifiers()
1393 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,  in hasModifiersSet()
1399 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,  in usesConstantBus()
1451 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,  in verifyInstruction()
1583 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {  in getVALUOp()
1646 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {  in isSALUOpSupportedOnVALU()
1650 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,  in getOpRegClass()
1667 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {  in canReadVGPR()
1679 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {  in legalizeOpWithMove()
1706 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,  in buildExtractSubReg()
1738 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(  in buildExtractSubRegOrImm()
1761 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {  in swapOperands()
1768 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,  in isLegalRegOperand()
1792 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,  in isLegalVSrcOperand()
1803 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,  in isOperandLegal()
1845 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,  in legalizeOperandsVOP2()
1924 void SIInstrInfo::legalizeOperandsVOP3(  in legalizeOperandsVOP3()
1963 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {  in legalizeOperands()
2234 void SIInstrInfo::splitSMRD(MachineInstr *MI,  in splitSMRD()
2337 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI,  in moveSMRDToVALU()
2445 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {  in moveToVALU()
2613 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,  in calculateIndirectAddress()
2619 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {  in getIndirectAddrRegClass()
2623 void SIInstrInfo::lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,  in lowerScalarAbs()
2647 void SIInstrInfo::splitScalar64BitUnaryOp(  in splitScalar64BitUnaryOp()
2701 void SIInstrInfo::splitScalar64BitBinaryOp(  in splitScalar64BitBinaryOp()
2769 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,  in splitScalar64BitBCNT()
2810 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,  in splitScalar64BitBFE()
2873 void SIInstrInfo::addUsersToMoveToVALUWorklist(  in addUsersToMoveToVALUWorklist()
2886 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(  in getDestEquivalentVGPRClass()
2911 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,  in findUsedSGPR()
2980 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(  in buildIndirectWrite()
2998 MachineInstrBuilder SIInstrInfo::buildIndirectRead(  in buildIndirectRead()
3016 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,  in reserveIndirectRegisters()
3044 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,  in getNamedOperand()
3053 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {  in getDefaultRsrcDataFormat()
3066 uint64_t SIInstrInfo::getScratchRsrcWords23() const {  in getScratchRsrcWords23()