Lines Matching refs:TIDReg
692 unsigned TIDReg = MFI->getTIDReg(); in calculateLDSSpillAddress() local
698 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass); in calculateLDSSpillAddress()
699 if (TIDReg == AMDGPU::NoRegister) in calculateLDSSpillAddress()
700 return TIDReg; in calculateLDSSpillAddress()
735 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg) in calculateLDSSpillAddress()
739 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg) in calculateLDSSpillAddress()
742 .addReg(TIDReg); in calculateLDSSpillAddress()
744 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg) in calculateLDSSpillAddress()
745 .addReg(TIDReg) in calculateLDSSpillAddress()
750 TIDReg) in calculateLDSSpillAddress()
755 TIDReg) in calculateLDSSpillAddress()
757 .addReg(TIDReg); in calculateLDSSpillAddress()
761 TIDReg) in calculateLDSSpillAddress()
763 .addReg(TIDReg); in calculateLDSSpillAddress()
764 MFI->setTIDReg(TIDReg); in calculateLDSSpillAddress()
771 .addReg(TIDReg); in calculateLDSSpillAddress()