818       assert(SrcOp.isReg());  in expandPostRAPseudo()
899   if (!Src0.isReg())  in commuteInstructionImpl()
927   if (!Src1.isReg()) {  in commuteInstructionImpl()
989   if (!MI->getOperand(Src0Idx).isReg())  in findCommutedOpIndices()
1002   } else if (Src1.isReg()) {  in findCommutedOpIndices()
1068     if (Src0->isReg() && Src0->getReg() == Reg) {  in FoldImmediate()
1069       if (!Src1->isReg() ||  in FoldImmediate()
1070           (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))  in FoldImmediate()
1073       if (!Src2->isReg() ||  in FoldImmediate()
1074           (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))  in FoldImmediate()
1127     if (Src2->isReg() && Src2->getReg() == Reg) {  in FoldImmediate()
1131           (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))  in FoldImmediate()
1134       if (!Src1->isReg() ||  in FoldImmediate()
1135           (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))  in FoldImmediate()
1406   if (!MO.isReg() || !MO.isUse())  in usesConstantBus()
1506     if (!MI->getOperand(i).isReg())  in verifyInstruction()
1540         if (MO.isReg()) {  in verifyInstruction()
1561     if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {  in verifyInstruction()
1591     return MI.getOperand(1).isReg() ?  in getVALUOp()
1687   if (MO.isReg())  in legalizeOpWithMove()
1771   if (!MO.isReg())  in isLegalRegOperand()
1795   if (MO.isReg())  in isLegalVSrcOperand()
1816         MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;  in isOperandLegal()
1821       if (Op.isReg() && Op.getReg() != SGPRUsed &&  in isOperandLegal()
1828   if (MO->isReg()) {  in isOperandLegal()
1864     if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg()))  in legalizeOperandsVOP2()
1890   if ((!Src1.isImm() && !Src1.isReg()) ||  in legalizeOperandsVOP2()
1910   else if (Src1.isReg()) {  in legalizeOperandsVOP2()
1945     if (!MO.isReg())  in legalizeOperandsVOP3()
1984       if (!MI->getOperand(i).isReg() ||  in legalizeOperands()
2012       if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))  in legalizeOperands()
2038         if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))  in legalizeOperands()
2352       if (MI->getOperand(2).isReg()) {  in moveSMRDToVALU()
2559       if (Op.isReg() && Op.getReg() == AMDGPU::SCC)  in moveToVALU()
2661   const TargetRegisterClass *Src0RC = Src0.isReg() ?  in splitScalar64BitUnaryOp()
2716   const TargetRegisterClass *Src0RC = Src0.isReg() ?  in splitScalar64BitBinaryOp()
2721   const TargetRegisterClass *Src1RC = Src1.isReg() ?  in splitScalar64BitBinaryOp()
2781   const TargetRegisterClass *SrcRC = Src.isReg() ?  in splitScalar64BitBCNT()
2937     if (!MO.isReg())  in findUsedSGPR()