29   unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
35   MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
68   unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
71   MachineInstr *commuteInstructionImpl(MachineInstr *MI,
83   bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
99                    MachineBasicBlock::iterator MI, DebugLoc DL,
104                                     MachineBasicBlock::iterator MI,
111                            MachineBasicBlock::iterator MI,
117                             MachineBasicBlock::iterator MI,
122   bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
130   int commuteOpcode(const MachineInstr &MI) const;
132   bool findCommutedOpIndices(MachineInstr *MI,
151                                       MachineBasicBlock::iterator &MI,
154   static bool isSALU(const MachineInstr &MI) {  in isSALU()  argument
155     return MI.getDesc().TSFlags & SIInstrFlags::SALU;  in isSALU()
162   static bool isVALU(const MachineInstr &MI) {  in isVALU()  argument
163     return MI.getDesc().TSFlags & SIInstrFlags::VALU;  in isVALU()
170   static bool isSOP1(const MachineInstr &MI) {  in isSOP1()  argument
171     return MI.getDesc().TSFlags & SIInstrFlags::SOP1;  in isSOP1()
178   static bool isSOP2(const MachineInstr &MI) {  in isSOP2()  argument
179     return MI.getDesc().TSFlags & SIInstrFlags::SOP2;  in isSOP2()
186   static bool isSOPC(const MachineInstr &MI) {  in isSOPC()  argument
187     return MI.getDesc().TSFlags & SIInstrFlags::SOPC;  in isSOPC()
194   static bool isSOPK(const MachineInstr &MI) {  in isSOPK()  argument
195     return MI.getDesc().TSFlags & SIInstrFlags::SOPK;  in isSOPK()
202   static bool isSOPP(const MachineInstr &MI) {  in isSOPP()  argument
203     return MI.getDesc().TSFlags & SIInstrFlags::SOPP;  in isSOPP()
210   static bool isVOP1(const MachineInstr &MI) {  in isVOP1()  argument
211     return MI.getDesc().TSFlags & SIInstrFlags::VOP1;  in isVOP1()
218   static bool isVOP2(const MachineInstr &MI) {  in isVOP2()  argument
219     return MI.getDesc().TSFlags & SIInstrFlags::VOP2;  in isVOP2()
226   static bool isVOP3(const MachineInstr &MI) {  in isVOP3()  argument
227     return MI.getDesc().TSFlags & SIInstrFlags::VOP3;  in isVOP3()
234   static bool isVOPC(const MachineInstr &MI) {  in isVOPC()  argument
235     return MI.getDesc().TSFlags & SIInstrFlags::VOPC;  in isVOPC()
242   static bool isMUBUF(const MachineInstr &MI) {  in isMUBUF()  argument
243     return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;  in isMUBUF()
250   static bool isMTBUF(const MachineInstr &MI) {  in isMTBUF()  argument
251     return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;  in isMTBUF()
258   static bool isSMRD(const MachineInstr &MI) {  in isSMRD()  argument
259     return MI.getDesc().TSFlags & SIInstrFlags::SMRD;  in isSMRD()
266   static bool isDS(const MachineInstr &MI) {  in isDS()  argument
267     return MI.getDesc().TSFlags & SIInstrFlags::DS;  in isDS()
274   static bool isMIMG(const MachineInstr &MI) {  in isMIMG()  argument
275     return MI.getDesc().TSFlags & SIInstrFlags::MIMG;  in isMIMG()
282   static bool isFLAT(const MachineInstr &MI) {  in isFLAT()  argument
283     return MI.getDesc().TSFlags & SIInstrFlags::FLAT;  in isFLAT()
290   static bool isWQM(const MachineInstr &MI) {  in isWQM()  argument
291     return MI.getDesc().TSFlags & SIInstrFlags::WQM;  in isWQM()
298   static bool isVGPRSpill(const MachineInstr &MI) {  in isVGPRSpill()  argument
299     return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;  in isVGPRSpill()
310   bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
326   bool hasModifiersSet(const MachineInstr &MI,
329   bool verifyInstruction(const MachineInstr *MI,
332   static unsigned getVALUOp(const MachineInstr &MI);
334   bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
341   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
360   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {  in getOpSize()  argument
361     return getOpRegClass(MI, OpNo)->getSize();  in getOpSize()
366   bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
377   void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
381   bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
399   void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr *MI) const;
402   void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr *MI) const;
406   void legalizeOperands(MachineInstr *MI) const;
410   void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
414   void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI,
420   void moveToVALU(MachineInstr &MI) const;
444   void insertWaitStates(MachineBasicBlock::iterator MI, int Count) const;
449   MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
452   const MachineOperand *getNamedOperand(const MachineInstr &MI,  in getNamedOperand()  argument
454     return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);  in getNamedOperand()
458   int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {  in getNamedImmOperand()  argument
459     int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);  in getNamedImmOperand()
460     return MI.getOperand(Idx).getImm();  in getNamedImmOperand()