Lines Matching refs:simm16

413   (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16"
418   (ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16"
424   (ins i32imm:$imm, u16imm:$simm16), " $imm, $simm16"
431 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
437   let simm16 = 0;
444   0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
445   [(br bb:$simm16)]> {
451   0x00000004, (ins sopp_brtarget:$simm16),
452   "s_cbranch_scc0 $simm16"
455   0x00000005, (ins sopp_brtarget:$simm16),
456   "s_cbranch_scc1 $simm16"
462   0x00000006, (ins sopp_brtarget:$simm16),
463   "s_cbranch_vccz $simm16"
466   0x00000007, (ins sopp_brtarget:$simm16),
467   "s_cbranch_vccnz $simm16"
473   0x00000008, (ins sopp_brtarget:$simm16),
474   "s_cbranch_execz $simm16"
477   0x00000009, (ins sopp_brtarget:$simm16),
478   "s_cbranch_execnz $simm16"
491   let simm16 = 0;
497 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">;
498 def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">;
499 def S_SLEEP : SOPP <0x0000000e, (ins i16imm:$simm16), "s_sleep $simm16">;
503   def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16), "s_sendmsg $simm16",
504       [(AMDGPUsendmsg (i32 imm:$simm16))]
508 def S_SENDMSGHALT : SOPP <0x00000011, (ins i16imm:$simm16), "s_sendmsghalt $simm16">;
509 def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">;
511 	let simm16 = 0;
513 def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">;
514 def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">;
516   let simm16 = 0;