95 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)  in ARMBaseInstrInfo()  function in ARMBaseInstrInfo
109 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,  in CreateTargetHazardRecognizer()
119 ScheduleHazardRecognizer *ARMBaseInstrInfo::
128 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,  in convertToThreeAddress()
278 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,  in AnalyzeBranch()
369 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {  in RemoveBranch()
394 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,  in InsertBranch()
434 bool ARMBaseInstrInfo::
441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {  in isPredicated()
457 bool ARMBaseInstrInfo::
478 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,  in SubsumesPredicate()
504 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,  in DefinesPredicate()
558 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {  in isPredicable()
597 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {  in GetInstSizeInBytes()
648 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {  in getInstBundleLength()
659 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,  in copyFromCPSR()
680 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,  in copyToCPSR()
702 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
834 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,  in AddDReg()
845 void ARMBaseInstrInfo::
980 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,  in isStoreToStackSlot()
1028 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,  in isStoreToStackSlotPostFE()
1034 void ARMBaseInstrInfo::
1168 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,  in isLoadFromStackSlot()
1216 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,  in isLoadFromStackSlotPostFE()
1224 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MBBI) const {  in expandMEMCPY()
1227   const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();  in expandMEMCPY()
1277 ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {  in expandPostRAPseudo()
1406 void ARMBaseInstrInfo::
1435 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {  in duplicate()
1450 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,  in produceSameValue()
1545 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,  in areLoadsFromSameBasePtr()
1626 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,  in shouldScheduleLoadsNear()
1656 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,  in isSchedulingBoundary()
1699 bool ARMBaseInstrInfo::
1742 bool ARMBaseInstrInfo::
1766 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,  in isProfitableToUnpredicate()
1800 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr *MI,  in commuteInstructionImpl()
1863 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,  in analyzeSelect()
1885 ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,  in optimizeSelect()
2000                                const ARMBaseInstrInfo &TII, unsigned MIFlags) {  in emitARMRegPlusImmediate()
2142                                 const ARMBaseInstrInfo &TII) {  in rewriteARMFrameIndex()
2284 bool ARMBaseInstrInfo::
2388 bool ARMBaseInstrInfo::
2636 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,  in FoldImmediate()
2997 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {  in getNumLDMAddresses()
3007 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,  in getNumMicroOps()
3151 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,  in getVLDMDefCycle()
3192 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,  in getLDMDefCycle()
3227 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,  in getVSTMUseCycle()
3267 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,  in getSTMUseCycle()
3296 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
3643 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
3733 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
3949 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {  in getPredicationCost()
3967 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
4017 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
4035 bool ARMBaseInstrInfo::
4056 bool ARMBaseInstrInfo::
4072 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,  in verifyInstruction()
4083 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,  in expandLoadStackGuardBase()
4114 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,  in isFpMLxInstruction()
4149 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {  in getExecutionDomain()
4241 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {  in setExecutionDomain()
4449 unsigned ARMBaseInstrInfo::
4511 void ARMBaseInstrInfo::
4546 bool ARMBaseInstrInfo::hasNOP() const {  in hasNOP()
4550 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {  in isSwiftFastImmShift()
4564 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(  in getRegSequenceLikeInputs()
4589 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(  in getExtractSubregLikeInputs()
4610 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(  in getInsertSubregLikeInputs()