834 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,  in AddDReg()  function in ARMBaseInstrInfo
881           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
882           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);  in storeRegToStackSlot()
892           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
893           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);  in storeRegToStackSlot()
928           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
929           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
930           AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
949           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
950           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
951           MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
952                 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);  in storeRegToStackSlot()
963         MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
964         MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
965         MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
966         MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);  in storeRegToStackSlot()
967         MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);  in storeRegToStackSlot()
968         MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);  in storeRegToStackSlot()
969         MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);  in storeRegToStackSlot()
970               AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);  in storeRegToStackSlot()
1069         AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1070         AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1079         MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1080         MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1113         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1114         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1115         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1133         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1134         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1135         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1136         MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1149       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1150       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1151       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1152       MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1153       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1154       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1155       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1156       MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()