509     if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||  in DefinesPredicate()
510         (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {  in DefinesPredicate()
521     if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())  in isCPSRDefined()
585     if (MO.getReg() != ARM::CPSR)  in IsCPSRDead()
677   MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));  in copyFromCPSR()
699   MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define);  in copyToCPSR()
789   } else if (SrcReg == ARM::CPSR) {  in copyPhysReg()
792   } else if (DestReg == ARM::CPSR) {  in copyPhysReg()
1811     if (CC == ARMCC::AL || PredReg != ARM::CPSR)  in commuteInstructionImpl()
2449     if (Instr.modifiesRegister(ARM::CPSR, TRI) ||  in optimizeCompareInstr()
2450         Instr.readsRegister(ARM::CPSR, TRI))  in optimizeCompareInstr()
2528         if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {  in optimizeCompareInstr()
2532         if (!MO.isReg() || MO.getReg() != ARM::CPSR)  in optimizeCompareInstr()
2614         if ((*SI)->isLiveIn(ARM::CPSR))  in optimizeCompareInstr()
2619     MI->getOperand(5).setReg(ARM::CPSR);  in optimizeCompareInstr()
2654     if (MO.getReg() == ARM::CPSR && !MO.isDead())  in FoldImmediate()
2663     if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)  in FoldImmediate()
3679   if (Reg == ARM::CPSR) {  in getOperandLatency()
3959   if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {  in getPredicationCost()
3988   if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {  in getInstrLatency()