Lines Matching refs:DestReg
661 unsigned DestReg, bool KillSrc, in copyFromCPSR() argument
668 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg); in copyFromCPSR()
704 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
706 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
710 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
715 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
725 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP()) in copyPhysReg()
727 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
731 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
745 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
749 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
754 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
758 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
762 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
766 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
770 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
775 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
780 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
785 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) { in copyPhysReg()
790 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget); in copyPhysReg()
792 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
803 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { in copyPhysReg()
811 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing); in copyPhysReg()
828 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
1036 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
1051 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) in loadRegFromStackSlot()
1055 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
1062 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
1069 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1070 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1079 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1080 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1083 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1084 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1091 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) in loadRegFromStackSlot()
1095 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) in loadRegFromStackSlot()
1105 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) in loadRegFromStackSlot()
1113 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1114 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1115 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1116 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1117 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1125 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) in loadRegFromStackSlot()
1133 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1134 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1135 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1136 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1137 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1138 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1149 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1150 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1151 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1152 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1153 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1154 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1155 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1156 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1157 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1158 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1409 unsigned DestReg, unsigned SubIdx, in reMaterialize() argument
1416 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1426 DestReg) in reMaterialize()
1900 unsigned DestReg = MI->getOperand(0).getReg(); in optimizeSelect() local
1902 if (!MRI.constrainRegClass(DestReg, PreviousClass)) in optimizeSelect()
1908 DefMI->getDesc(), DestReg); in optimizeSelect()
1998 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitARMRegPlusImmediate() argument
2001 if (NumBytes == 0 && DestReg != BaseReg) { in emitARMRegPlusImmediate()
2002 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) in emitARMRegPlusImmediate()
2024 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitARMRegPlusImmediate()
2028 BaseReg = DestReg; in emitARMRegPlusImmediate()