Lines Matching refs:UseIdx
3230 unsigned UseIdx, unsigned UseAlign) const { in getVSTMUseCycle() argument
3231 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getVSTMUseCycle()
3233 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
3270 unsigned UseIdx, unsigned UseAlign) const { in getSTMUseCycle() argument
3271 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getSTMUseCycle()
3273 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
3300 unsigned UseIdx, unsigned UseAlign) const { in getOperandLatency() argument
3304 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
3305 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
3355 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
3364 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); in getOperandLatency()
3382 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); in getOperandLatency()
3396 UseClass, UseIdx)) in getOperandLatency()
3399 UseClass, UseIdx)) { in getOperandLatency()
3432 unsigned &UseIdx, unsigned &Dist) { in getBundledUseMI() argument
3455 UseIdx = Idx; in getBundledUseMI()
3646 unsigned UseIdx) const { in getOperandLatency()
3675 UseIdx = NewUseIdx; in getOperandLatency()
3705 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit()) in getOperandLatency()
3715 *UseMCID, UseIdx, UseAlign); in getOperandLatency()
3735 SDNode *UseNode, unsigned UseIdx) const { in getOperandLatency()
3763 UseMCID, UseIdx, UseAlign); in getOperandLatency()
4039 const MachineInstr *UseMI, unsigned UseIdx) const { in hasHighOperandLatency()
4049 = SchedModel.computeOperandLatency(DefMI, DefIdx, UseMI, UseIdx); in hasHighOperandLatency()