Lines Matching refs:Op0IsKill
108 unsigned Op0, bool Op0IsKill);
111 unsigned Op0, bool Op0IsKill,
115 unsigned Op0, bool Op0IsKill,
120 unsigned Op0, bool Op0IsKill,
124 unsigned Op0, bool Op0IsKill,
286 unsigned Op0, bool Op0IsKill) { in fastEmitInst_r() argument
295 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
298 .addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
308 unsigned Op0, bool Op0IsKill, in fastEmitInst_rr() argument
321 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
325 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
336 unsigned Op0, bool Op0IsKill, in fastEmitInst_rrr() argument
351 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rrr()
356 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rrr()
368 unsigned Op0, bool Op0IsKill, in fastEmitInst_ri() argument
379 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_ri()
383 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_ri()
394 unsigned Op0, bool Op0IsKill, in fastEmitInst_rri() argument
407 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rri()
412 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rri()