Lines Matching refs:Opc
474 unsigned Opc; in ARMMaterializeFP() local
477 Opc = ARM::FCONSTD; in ARMMaterializeFP()
480 Opc = ARM::FCONSTS; in ARMMaterializeFP()
484 TII.get(Opc), DestReg).addImm(Imm)); in ARMMaterializeFP()
499 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) in ARMMaterializeFP()
518 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
523 TII.get(Opc), ImmReg) in ARMMaterializeInt()
534 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
539 TII.get(Opc), ImmReg) in ARMMaterializeInt()
598 unsigned Opc; in ARMMaterializeGV() local
605 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel; in ARMMaterializeGV()
608 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm; in ARMMaterializeGV()
612 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF)); in ARMMaterializeGV()
636 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; in ARMMaterializeGV() local
637 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), in ARMMaterializeGV()
652 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; in ARMMaterializeGV() local
656 DbgLoc, TII.get(Opc), NewDestReg) in ARMMaterializeGV()
717 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in fastMaterializeAlloca() local
720 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
723 TII.get(Opc), ResultReg) in fastMaterializeAlloca()
895 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress() local
897 TII.get(Opc), ResultReg) in ARMSimplifyAddress()
960 unsigned Opc; in ARMEmitLoad() local
971 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; in ARMEmitLoad()
973 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12; in ARMEmitLoad()
976 Opc = ARM::LDRBi12; in ARMEmitLoad()
978 Opc = ARM::LDRSB; in ARMEmitLoad()
990 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; in ARMEmitLoad()
992 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12; in ARMEmitLoad()
994 Opc = isZExt ? ARM::LDRH : ARM::LDRSH; in ARMEmitLoad()
1005 Opc = ARM::t2LDRi8; in ARMEmitLoad()
1007 Opc = ARM::t2LDRi12; in ARMEmitLoad()
1009 Opc = ARM::LDRi12; in ARMEmitLoad()
1019 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; in ARMEmitLoad()
1022 Opc = ARM::VLDRS; in ARMEmitLoad()
1033 Opc = ARM::VLDRD; in ARMEmitLoad()
1045 TII.get(Opc), ResultReg); in ARMEmitLoad()
1091 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; in ARMEmitStore() local
1092 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
1094 TII.get(Opc), Res) in ARMEmitStore()
1347 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX; in SelectIndirectBr() local
1349 TII.get(Opc)).addReg(AddrReg)); in SelectIndirectBr()
1575 unsigned Opc; in SelectIToFP() local
1576 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS; in SelectIToFP()
1577 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD; in SelectIToFP()
1582 TII.get(Opc), ResultReg).addReg(FP)); in SelectIToFP()
1599 unsigned Opc; in SelectFPToI() local
1601 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS; in SelectFPToI()
1602 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD; in SelectFPToI()
1608 TII.get(Opc), ResultReg).addReg(Op)); in SelectFPToI()
1753 unsigned Opc; in SelectBinaryIntOp() local
1757 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr; in SelectBinaryIntOp()
1760 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr; in SelectBinaryIntOp()
1763 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr; in SelectBinaryIntOp()
1776 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
1777 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
1779 TII.get(Opc), ResultReg) in SelectBinaryIntOp()
1803 unsigned Opc; in SelectBinaryFPOp() local
1808 Opc = is64bit ? ARM::VADDD : ARM::VADDS; in SelectBinaryFPOp()
1811 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS; in SelectBinaryFPOp()
1814 Opc = is64bit ? ARM::VMULD : ARM::VMULS; in SelectBinaryFPOp()
1825 TII.get(Opc), ResultReg) in SelectBinaryFPOp()
2620 uint32_t Opc : 16; in ARMEmitIntExt() member
2679 unsigned Opc = ITP->Opc; in ARMEmitIntExt() local
2680 assert(ARM::KILL != Opc && "Invalid table entry"); in ARMEmitIntExt()
2683 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) && in ARMEmitIntExt()
2708 unsigned Opcode = isLsl ? LSLOpc : Opc; in ARMEmitIntExt()
2764 unsigned Opc = ARM::MOVsr; in SelectShift() local
2775 Opc = ARM::MOVsi; in SelectShift()
2783 if (Opc == ARM::MOVsr) { in SelectShift()
2792 TII.get(Opc), ResultReg) in SelectShift()
2795 if (Opc == ARM::MOVsi) in SelectShift()
2797 else if (Opc == ARM::MOVsr) { in SelectShift()
2884 uint16_t Opc[2]; // ARM, Thumb. member
2920 if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() && in tryToFoldLoadIntoMI()
2958 unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp; in ARMLowerPICELF() local
2960 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg) in ARMLowerPICELF()
2962 if (Opc == ARM::LDRcp) in ARMLowerPICELF()
2968 Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR in ARMLowerPICELF()
2970 DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0); in ARMLowerPICELF()
2971 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) in ARMLowerPICELF()