Lines Matching refs:ResultReg
171 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
287 unsigned ResultReg = createResultReg(RC); in fastEmitInst_r() local
295 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
300 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_r()
303 return ResultReg; in fastEmitInst_r()
310 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rr() local
320 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rr()
328 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rr()
331 return ResultReg; in fastEmitInst_rr()
339 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rrr() local
350 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rrr()
360 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rrr()
363 return ResultReg; in fastEmitInst_rrr()
370 unsigned ResultReg = createResultReg(RC); in fastEmitInst_ri() local
378 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_ri()
386 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_ri()
389 return ResultReg; in fastEmitInst_ri()
397 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rri() local
406 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rri()
416 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rri()
419 return ResultReg; in fastEmitInst_rri()
425 unsigned ResultReg = createResultReg(RC); in fastEmitInst_i() local
430 ResultReg).addImm(Imm)); in fastEmitInst_i()
435 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_i()
438 return ResultReg; in fastEmitInst_i()
545 unsigned ResultReg = 0; in ARMMaterializeInt() local
547 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); in ARMMaterializeInt()
549 if (ResultReg) in ARMMaterializeInt()
550 return ResultReg; in ARMMaterializeInt()
563 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
566 TII.get(ARM::t2LDRpci), ResultReg) in ARMMaterializeInt()
570 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
572 TII.get(ARM::LDRcp), ResultReg) in ARMMaterializeInt()
576 return ResultReg; in ARMMaterializeInt()
719 unsigned ResultReg = createResultReg(RC); in fastMaterializeAlloca() local
720 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
723 TII.get(Opc), ResultReg) in fastMaterializeAlloca()
726 return ResultReg; in fastMaterializeAlloca()
894 unsigned ResultReg = createResultReg(RC); in ARMSimplifyAddress() local
897 TII.get(Opc), ResultReg) in ARMSimplifyAddress()
900 Addr.Base.Reg = ResultReg; in ARMSimplifyAddress()
958 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in ARMEmitLoad() argument
1042 ResultReg = createResultReg(RC); in ARMEmitLoad()
1043 assert (ResultReg > 255 && "Expected an allocated virtual register."); in ARMEmitLoad()
1045 TII.get(Opc), ResultReg); in ARMEmitLoad()
1054 .addReg(ResultReg)); in ARMEmitLoad()
1055 ResultReg = MoveReg; in ARMEmitLoad()
1074 unsigned ResultReg; in SelectLoad() local
1075 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment())) in SelectLoad()
1077 updateValueMap(I, ResultReg); in SelectLoad()
1580 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP() local
1582 TII.get(Opc), ResultReg).addReg(FP)); in SelectIToFP()
1583 updateValueMap(I, ResultReg); in SelectIToFP()
1606 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); in SelectFPToI() local
1608 TII.get(Opc), ResultReg).addReg(Op)); in SelectFPToI()
1612 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
1672 unsigned ResultReg = createResultReg(RC); in SelectSelect() local
1677 ResultReg) in SelectSelect()
1685 ResultReg) in SelectSelect()
1691 updateValueMap(I, ResultReg); in SelectSelect()
1775 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectBinaryIntOp() local
1779 TII.get(Opc), ResultReg) in SelectBinaryIntOp()
1781 updateValueMap(I, ResultReg); in SelectBinaryIntOp()
1823 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp() local
1825 TII.get(Opc), ResultReg) in SelectBinaryFPOp()
1827 updateValueMap(I, ResultReg); in SelectBinaryFPOp()
2044 unsigned ResultReg = createResultReg(DstRC); in FinishCall() local
2046 TII.get(ARM::VMOVDRR), ResultReg) in FinishCall()
2054 updateValueMap(I, ResultReg); in FinishCall()
2065 unsigned ResultReg = createResultReg(DstRC); in FinishCall() local
2068 ResultReg).addReg(RVLocs[0].getLocReg()); in FinishCall()
2072 updateValueMap(I, ResultReg); in FinishCall()
2461 unsigned ResultReg; in ARMTryEmitSmallMemCpy() local
2462 RV = ARMEmitLoad(VT, ResultReg, Src); in ARMTryEmitSmallMemCpy()
2464 RV = ARMEmitStore(VT, ResultReg, Dest); in ARMTryEmitSmallMemCpy()
2690 unsigned ResultReg; in ARMEmitIntExt() local
2706 ResultReg = createResultReg(RC); in ARMEmitIntExt()
2713 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg); in ARMEmitIntExt()
2721 SrcReg = ResultReg; in ARMEmitIntExt()
2724 return ResultReg; in ARMEmitIntExt()
2746 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); in SelectIntExt() local
2747 if (ResultReg == 0) return false; in SelectIntExt()
2748 updateValueMap(I, ResultReg); in SelectIntExt()
2788 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectShift() local
2789 if(ResultReg == 0) return false; in SelectShift()
2792 TII.get(Opc), ResultReg) in SelectShift()
2803 updateValueMap(I, ResultReg); in SelectShift()
2933 unsigned ResultReg = MI->getOperand(0).getReg(); in tryToFoldLoadIntoMI() local
2934 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false)) in tryToFoldLoadIntoMI()
3052 unsigned ResultReg = createResultReg(RC); in fastLowerArguments() local
3055 ResultReg).addReg(DstReg, getKillRegState(true)); in fastLowerArguments()
3056 updateValueMap(&*I, ResultReg); in fastLowerArguments()