Lines Matching refs:SrcReg1
1431 unsigned SrcReg1 = getRegForValue(Src1Value); in ARMEmitCmp() local
1432 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1442 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1443 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1451 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp()
1455 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1459 .addReg(SrcReg1); in ARMEmitCmp()
1767 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local
1768 if (SrcReg1 == 0) return false; in SelectBinaryIntOp()
1776 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
1780 .addReg(SrcReg1).addReg(SrcReg2)); in SelectBinaryIntOp()