292   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_r()
315   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_rr()
316   Op1 = constrainOperandRegClass(II, Op1, 2);  in fastEmitInst_rr()
344   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_rrr()
345   Op1 = constrainOperandRegClass(II, Op1, 2);  in fastEmitInst_rrr()
346   Op2 = constrainOperandRegClass(II, Op1, 3);  in fastEmitInst_rrr()
375   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_ri()
402   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_rri()
403   Op1 = constrainOperandRegClass(II, Op1, 2);  in fastEmitInst_rri()
570     ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);  in ARMMaterializeInt()
644       DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);  in ARMMaterializeGV()
720     ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);  in fastMaterializeAlloca()
1092       SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);  in ARMEmitStore()
1164   SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);  in ARMEmitStore()
1287       OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);  in SelectBranch()
1324   CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);  in SelectBranch()
1451   SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);  in ARMEmitCmp()
1453     SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);  in ARMEmitCmp()
1654   CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);  in SelectSelect()
1674     Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);  in SelectSelect()
1675     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);  in SelectSelect()
1683     Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);  in SelectSelect()
1776   SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);  in SelectBinaryIntOp()
1777   SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);  in SelectBinaryIntOp()
2716     SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);  in ARMEmitIntExt()
2970   DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);  in ARMLowerPICELF()