Lines Matching refs:Opc
114 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
117 SDValue &Offset, SDValue &Opc);
119 SDValue &Opc) { in SelectAddrMode2Base() argument
120 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE; in SelectAddrMode2Base()
124 SDValue &Opc) { in SelectAddrMode2ShOp() argument
125 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP; in SelectAddrMode2ShOp()
129 SDValue &Opc) { in SelectAddrMode2() argument
130 SelectAddrMode2Worker(N, Base, Offset, Opc); in SelectAddrMode2()
144 SDValue &Offset, SDValue &Opc);
146 SDValue &Offset, SDValue &Opc);
148 SDValue &Offset, SDValue &Opc);
151 SDValue &Offset, SDValue &Opc);
153 SDValue &Offset, SDValue &Opc);
240 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
312 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { in isOpcWithIntImmediate() argument
313 return N->getOpcode() == Opc && in isOpcWithIntImmediate()
540 SDValue &Opc, in SelectImmShifterOperand() argument
556 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ARM_AM::lsl, in SelectImmShifterOperand()
574 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), in SelectImmShifterOperand()
582 SDValue &Opc, in SelectRegShifterOperand() argument
601 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), in SelectRegShifterOperand()
659 SDValue &Opc) { in SelectLdStSOReg() argument
675 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, in SelectLdStSOReg()
759 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), in SelectLdStSOReg()
770 SDValue &Opc) { in SelectAddrMode2Worker() argument
786 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, in SelectAddrMode2Worker()
808 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0, in SelectAddrMode2Worker()
832 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC, in SelectAddrMode2Worker()
843 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0, in SelectAddrMode2Worker()
899 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), in SelectAddrMode2Worker()
905 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetReg() argument
935 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), in SelectAddrMode2OffsetReg()
941 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetImmPre() argument
952 Opc = CurDAG->getTargetConstant(Val, SDLoc(Op), MVT::i32); in SelectAddrMode2OffsetImmPre()
961 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetImm() argument
971 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val, in SelectAddrMode2OffsetImm()
987 SDValue &Opc) { in SelectAddrMode3() argument
992 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0), SDLoc(N), in SelectAddrMode3()
1005 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N), in SelectAddrMode3()
1027 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC), SDLoc(N), in SelectAddrMode3()
1034 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N), in SelectAddrMode3()
1040 SDValue &Offset, SDValue &Opc) { in SelectAddrMode3Offset() argument
1050 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), SDLoc(Op), in SelectAddrMode3Offset()
1056 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), SDLoc(Op), in SelectAddrMode3Offset()
1702 static bool isVLDfixed(unsigned Opc) in isVLDfixed() argument
1704 switch (Opc) { in isVLDfixed()
1729 static bool isVSTfixed(unsigned Opc) in isVSTfixed() argument
1731 switch (Opc) { in isVSTfixed()
1754 static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) { in getVLDSTRegisterUpdateOpcode() argument
1755 assert((isVLDfixed(Opc) || isVSTfixed(Opc)) in getVLDSTRegisterUpdateOpcode()
1757 switch (Opc) { in getVLDSTRegisterUpdateOpcode()
1801 return Opc; // If not one we handle, return it unchanged. in getVLDSTRegisterUpdateOpcode()
1863 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD() local
1872 Opc = getVLDSTRegisterUpdateOpcode(Opc); in SelectVLD()
1875 if ((NumVecs > 2 && !isVLDfixed(Opc)) || in SelectVLD()
1882 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLD()
2014 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVST() local
2023 Opc = getVLDSTRegisterUpdateOpcode(Opc); in SelectVST()
2028 else if (NumVecs > 2 && !isVSTfixed(Opc)) in SelectVST()
2035 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVST()
2182 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLDSTLane() local
2184 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLDSTLane()
2246 unsigned Opc = Opcodes[OpcodeIndex]; in SelectVLDDup() local
2270 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLDDup()
2287 unsigned Opc) { in SelectVTBL() argument
2316 return CurDAG->getMachineNode(Opc, dl, VT, Ops); in SelectVTBL()
2324 unsigned Opc = isSigned in SelectV6T2BitfieldExtractOp() local
2352 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri; in SelectV6T2BitfieldExtractOp()
2356 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in SelectV6T2BitfieldExtractOp()
2373 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in SelectV6T2BitfieldExtractOp()
2396 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in SelectV6T2BitfieldExtractOp()
2415 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in SelectV6T2BitfieldExtractOp()
2552 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? in Select() local
2557 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in Select()
2624 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2()) in Select() local
2627 if (!Opc) in Select()
2647 return CurDAG->getMachineNode(Opc, dl, VT, Ops); in Select()
2744 unsigned Opc = Subtarget->isThumb() ? in Select() local
2759 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other, in Select()
2771 unsigned Opc = 0; in Select() local
2775 case MVT::v8i8: Opc = ARM::VZIPd8; break; in Select()
2776 case MVT::v4i16: Opc = ARM::VZIPd16; break; in Select()
2779 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
2780 case MVT::v16i8: Opc = ARM::VZIPq8; break; in Select()
2781 case MVT::v8i16: Opc = ARM::VZIPq16; break; in Select()
2783 case MVT::v4i32: Opc = ARM::VZIPq32; break; in Select()
2788 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops); in Select()
2791 unsigned Opc = 0; in Select() local
2795 case MVT::v8i8: Opc = ARM::VUZPd8; break; in Select()
2796 case MVT::v4i16: Opc = ARM::VUZPd16; break; in Select()
2799 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
2800 case MVT::v16i8: Opc = ARM::VUZPq8; break; in Select()
2801 case MVT::v8i16: Opc = ARM::VUZPq16; break; in Select()
2803 case MVT::v4i32: Opc = ARM::VUZPq32; break; in Select()
2808 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops); in Select()
2811 unsigned Opc = 0; in Select() local
2815 case MVT::v8i8: Opc = ARM::VTRNd8; break; in Select()
2816 case MVT::v4i16: Opc = ARM::VTRNd16; break; in Select()
2818 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
2819 case MVT::v16i8: Opc = ARM::VTRNq8; break; in Select()
2820 case MVT::v8i16: Opc = ARM::VTRNq16; break; in Select()
2822 case MVT::v4i32: Opc = ARM::VTRNq32; break; in Select()
2827 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops); in Select()