261   SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
262   SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
263   SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
264   SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
267   SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
268   SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
269   SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1592 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {  in createGPRPairNode()  argument
1593   SDLoc dl(V0.getNode());  in createGPRPairNode()
1598   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createGPRPairNode()
1603 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createSRegPairNode()  argument
1604   SDLoc dl(V0.getNode());  in createSRegPairNode()
1609   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createSRegPairNode()
1614 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createDRegPairNode()  argument
1615   SDLoc dl(V0.getNode());  in createDRegPairNode()
1620   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createDRegPairNode()
1625 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {  in createQRegPairNode()  argument
1626   SDLoc dl(V0.getNode());  in createQRegPairNode()
1631   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };  in createQRegPairNode()
1636 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadSRegsNode()  argument
1638   SDLoc dl(V0.getNode());  in createQuadSRegsNode()
1645   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadSRegsNode()
1651 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadDRegsNode()  argument
1653   SDLoc dl(V0.getNode());  in createQuadDRegsNode()
1660   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadDRegsNode()
1666 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,  in createQuadQRegsNode()  argument
1668   SDLoc dl(V0.getNode());  in createQuadQRegsNode()
1675   const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,  in createQuadQRegsNode()
1994       SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVST()  local
1997         SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);  in SelectVST()
2005         SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVST()
2047   SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVST()  local
2053   SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);  in SelectVST()
2159   SDValue V0 = N->getOperand(Vec0Idx + 0);  in SelectVLDSTLane()  local
2163       SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);  in SelectVLDSTLane()
2165       SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);  in SelectVLDSTLane()
2172       SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVLDSTLane()
2174       SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);  in SelectVLDSTLane()
2295   SDValue V0 = N->getOperand(FirstTblReg + 0);  in SelectVTBL()  local
2298     RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);  in SelectVTBL()
2306     RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);  in SelectVTBL()
3335     SDValue V0 = N->getOperand(0);  in Select()  local
3337     SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);  in Select()
3832     SDValue V0 = N->getOperand(i+1);  in SelectInlineAsm()  local
3834     unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();  in SelectInlineAsm()