88 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,  in addTypeForNEON()
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {  in addDRTypeForNEON()
157 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {  in addQRTypeForNEON()
162 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,  in ARMTargetLowering()  function in ARMTargetLowering
1047 bool ARMTargetLowering::useSoftFloat() const {  in useSoftFloat()
1062 ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,  in findRepresentativeClass()
1099 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
1234 EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,  in getSetCCResultType()
1243 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {  in getRegClassFor()
1259 bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,  in shouldAlignPointerArgs()
1272 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,  in createFastISel()
1277 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {  in getSchedulingPreference()
1367 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,  in getEffectiveCallingConv()
1401 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,  in CCAssignFnForNode()
1423 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,  in LowerCallResult()
1509 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,  in LowerMemOpCallTo()
1524 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,  in PassF64ArgInRegs()
1555 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,  in LowerCall()
1973 void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,  in HandleByVal()
2075 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,  in IsEligibleForTailCallOptimization()
2217 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,  in CanLowerReturn()
2261 ARMTargetLowering::LowerReturn(SDValue Chain,  in LowerReturn()
2372 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {  in isUsedByReturnOnly()
2447 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {  in mayBeEmittedAsTailCall()
2498 unsigned ARMTargetLowering::getJumpTableEncoding() const {  in getJumpTableEncoding()
2502 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,  in LowerBlockAddress()
2535 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,  in LowerToTLSGeneralDynamicModel()
2578 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,  in LowerToTLSExecModels()
2633 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {  in LowerGlobalTLSAddress()
2654 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,  in LowerGlobalAddressELF()
2707 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,  in LowerGlobalAddressDarwin()
2732 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,  in LowerGlobalAddressWindows()
2760 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {  in LowerEH_SJLJ_SETJMP()
2769 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {  in LowerEH_SJLJ_LONGJMP()
2775 SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,  in LowerEH_SJLJ_SETUP_DISPATCH()
2783 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,  in LowerINTRINSIC_WO_CHAIN()
2937 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,  in GetF64FormalArgument()
2982 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,  in StoreByValRegs()
3039 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,  in VarArgStyleRegisters()
3059 ARMTargetLowering::LowerFormalArguments(SDValue Chain,  in LowerFormalArguments()
3291 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,  in getARMCmp()
3350 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,  in getVFPCmp()
3364 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {  in duplicateCmp()
3383 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,  in getARMXALUOOp()
3427 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {  in LowerXALUO()
3450 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {  in LowerSELECT()
3568 SDValue ARMTargetLowering::getCMOV(SDLoc dl, EVT VT, SDValue FalseVal,  in getCMOV()
3594 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {  in LowerSELECT_CC()
3746 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {  in OptimizeVFPBrcond()
3796 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {  in LowerBR_CC()
3851 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {  in LowerBR_JT()
3908 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {  in LowerFP_TO_INT()
3960 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {  in LowerINT_TO_FP()
3979 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {  in LowerFCOPYSIGN()
4061 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{  in LowerRETURNADDR()
4085 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {  in LowerFRAMEADDR()
4106 unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,  in getRegisterByName()
4254 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,  in LowerShiftRightParts()
4290 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,  in LowerShiftLeftParts()
4322 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,  in LowerFLT_ROUNDS_()
4886 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,  in LowerConstantFP()
5360 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,  in LowerBUILD_VECTOR()
5569 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,  in ReconstructShuffle()
5775 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,  in isShuffleMaskLegal()
6632 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {  in LowerFSINCOS()
6708 SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,  in LowerWindowsDIVLibCall()
6727   ARMTargetLowering::ArgListTy Args;  in LowerWindowsDIVLibCall()
6745 SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,  in LowerDIV_Windows()
6757 void ARMTargetLowering::ExpandDIV_Windows(  in ExpandDIV_Windows()
6820 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {  in LowerOperation()
6905 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,  in ReplaceNodeResults()
6945 void ARMTargetLowering::
7060 void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr *MI,  in EmitSjLjDispatchBlock()
7558 ARMTargetLowering::EmitStructByval(MachineInstr *MI,  in EmitStructByval()
7792 ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,  in EmitLowered__chkstk()
7858 ARMTargetLowering::EmitLowered__dbzchk(MachineInstr *MI,  in EmitLowered__dbzchk()
7884 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,  in EmitInstrWithCustomInserter()
8168 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,  in AdjustInstrPostInstrSelection()
10403 SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &DAG) const {  in PerformCMOVToBFICombine()
10496 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {  in PerformCMOVCombine()
10565 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
10629 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,  in isDesirableToTransformToIntegerOp()
10634 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,  in allowsMisalignedMemoryAccesses()
10676 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,  in getOptimalMemOpType()
10709 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {  in isZExtFree()
10730 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {  in isVectorLoadExtDesirable()
10752 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {  in allowTruncateForTailCall()
10864 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,  in isLegalT2ScaledAddressingMode()
10899 bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,  in isLegalAddressingMode()
10963 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {  in isLegalICmpImmediate()
10977 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {  in isLegalAddImmediate()
11076 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,  in getPreIndexedAddressParts()
11114 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,  in getPostIndexedAddressParts()
11162 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,  in computeKnownBitsForTargetNode()
11212 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {  in ExpandInlineAsm()
11245 ARMTargetLowering::ConstraintType
11246 ARMTargetLowering::getConstraintType(StringRef Constraint) const {  in getConstraintType()
11274 ARMTargetLowering::getSingleConstraintMatchWeight(  in getSingleConstraintMatchWeight()
11305 RCPair ARMTargetLowering::getRegForInlineAsmConstraint(  in getRegForInlineAsmConstraint()
11356 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,  in LowerAsmOperandForConstraint()
11560 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {  in LowerDivRem()
11594 SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG) const {  in LowerREM()
11634 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {  in LowerDYNAMIC_STACKALLOC()
11659 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {  in LowerFP_EXTEND()
11671 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {  in LowerFP_ROUND()
11685 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {  in isOffsetFoldingLegal()
11702 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {  in isFPImmLegal()
11715 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,  in getTgtMemIntrinsic()
11828 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,  in shouldConvertConstantLoadToIntImm()
11838 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,  in makeDMB()
11868 Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,  in emitLeadingFence()
11896 Instruction* ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,  in emitTrailingFence()
11921 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {  in shouldExpandAtomicStoreInIR()
11934 ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {  in shouldExpandAtomicLoadInIR()
11943 ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {  in shouldExpandAtomicRMWInIR()
11950 bool ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(  in shouldExpandAtomicCmpXchgInIR()
11956 bool ARMTargetLowering::useLoadStackGuardNode() const {  in useLoadStackGuardNode()
11960 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,  in canCombineStoreAndExtract()
11989 bool ARMTargetLowering::isCheapToSpeculateCttz() const {  in isCheapToSpeculateCttz()
11993 bool ARMTargetLowering::isCheapToSpeculateCtlz() const {  in isCheapToSpeculateCtlz()
11997 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,  in emitLoadLinked()
12033 void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(  in emitAtomicCmpXchgNoStoreLLBalance()
12041 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,  in emitStoreConditional()
12085 bool ARMTargetLowering::lowerInterleavedLoad(  in lowerInterleavedLoad()
12173 bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,  in lowerInterleavedStore()
12299 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(  in functionArgumentNeedsConsecutiveRegisters()
12314 unsigned ARMTargetLowering::getExceptionPointerRegister(  in getExceptionPointerRegister()
12321 unsigned ARMTargetLowering::getExceptionSelectorRegister(  in getExceptionSelectorRegister()