Lines Matching refs:BITCAST
890 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in ARMTargetLowering()
1497 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1646 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
2300 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
2415 } else if (Copy->getOpcode() == ISD::BITCAST) { in isUsedByReturnOnly()
3192 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3276 } else if (Op->getOpcode() == ISD::BITCAST && in isFloatingPointZero()
3986 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
3998 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), in LowerFCOPYSIGN()
4006 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
4010 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), in LowerFCOPYSIGN()
4012 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
4013 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
4019 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
4025 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); in LowerFCOPYSIGN()
4029 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); in LowerFCOPYSIGN()
4039 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); in LowerFCOPYSIGN()
4047 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
4048 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, in LowerFCOPYSIGN()
4182 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc); in CombineVMOVDRRCandidateWithVecOp()
4215 return DAG.getNode(ISD::BITCAST, dl, DstVT, in ExpandBITCAST()
4249 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in getZeroVector()
4394 SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits); in LowerCTTZ()
4444 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0)); in getCTPOP16BitCounts()
4502 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0)); in lowerCTPOP32BitElements()
4691 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) in LowerVSETCC()
4696 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0)); in LowerVSETCC()
4697 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1)); in LowerVSETCC()
4942 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); in LowerConstantFP()
4945 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, in LowerConstantFP()
4959 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); in LowerConstantFP()
4962 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, in LowerConstantFP()
5379 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
5390 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
5503 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, in LowerBUILD_VECTOR()
5509 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerBUILD_VECTOR()
5541 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); in LowerBUILD_VECTOR()
5543 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerBUILD_VECTOR()
5713 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec); in ReconstructShuffle()
5767 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); in ReconstructShuffle()
6077 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); in LowerVECTOR_SHUFFLE()
6078 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); in LowerVECTOR_SHUFFLE()
6090 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerVECTOR_SHUFFLE()
6141 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), in LowerCONCAT_VECTORS()
6145 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), in LowerCONCAT_VECTORS()
6147 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); in LowerCONCAT_VECTORS()
6157 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { in isExtendedBUILD_VECTOR()
6303 if (N->getOpcode() == ISD::BITCAST) { in SkipExtensionForVMULL()
6422 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
6424 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
6448 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
6452 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
6487 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6491 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
6599 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerUDIV()
6603 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerUDIV()
6856 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG); in LowerOperation()
6915 case ISD::BITCAST: in ReplaceNodeResults()
8832 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); in PerformANDCombine()
8834 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); in PerformANDCombine()
8875 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); in PerformORCombine()
8877 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); in PerformORCombine()
8924 return DAG.getNode(ISD::BITCAST, dl, VT, Result); in PerformORCombine()
9249 if (Op0.getOpcode() == ISD::BITCAST) in PerformVMOVDRRCombine()
9251 if (Op1.getOpcode() == ISD::BITCAST) in PerformVMOVDRRCombine()
9256 return DAG.getNode(ISD::BITCAST, SDLoc(N), in PerformVMOVDRRCombine()
9300 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); in PerformBUILD_VECTORCombine()
9307 return DAG.getNode(ISD::BITCAST, dl, VT, BV); in PerformBUILD_VECTORCombine()
9337 if (Use->getOpcode() != ISD::BITCAST || in PerformARMBUILD_VECTORCombine()
9351 if (Elt->getOpcode() == ISD::BITCAST) { in PerformARMBUILD_VECTORCombine()
9384 if (V.getOpcode() == ISD::BITCAST && in PerformARMBUILD_VECTORCombine()
9389 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V); in PerformARMBUILD_VECTORCombine()
9396 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec); in PerformARMBUILD_VECTORCombine()
9418 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); in PerformInsertEltCombine()
9419 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); in PerformInsertEltCombine()
9425 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); in PerformInsertEltCombine()
9663 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal); in CombineBaseUpdate()
9679 LdVal = DAG.getNode(ISD::BITCAST, dl, VecTy, LdVal); in CombineBaseUpdate()
9793 while (Op.getOpcode() == ISD::BITCAST) in PerformVDUPLANECombine()
9809 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); in PerformVDUPLANECombine()
9862 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal); in PerformSTORECombine()
9892 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff); in PerformSTORECombine()
9949 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); in PerformSTORECombine()
9953 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); in PerformSTORECombine()
10092 while (Op.getOpcode() == ISD::BITCAST) in getVShiftImm()