Lines Matching refs:Rd
1224 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1231 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1232 iii, opc, "\t$Rd, $Rn, $imm",
1233 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1235 bits<4> Rd;
1240 let Inst{15-12} = Rd;
1244 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1245 iir, opc, "\t$Rd, $Rn, $Rm",
1246 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1248 bits<4> Rd;
1254 let Inst{15-12} = Rd;
1259 def rsi : AsI1<opcod, (outs GPR:$Rd),
1261 iis, opc, "\t$Rd, $Rn, $shift",
1262 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1264 bits<4> Rd;
1269 let Inst{15-12} = Rd;
1275 def rsr : AsI1<opcod, (outs GPR:$Rd),
1277 iis, opc, "\t$Rd, $Rn, $shift",
1278 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1280 bits<4> Rd;
1285 let Inst{15-12} = Rd;
1297 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1304 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1305 iii, opc, "\t$Rd, $Rn, $imm",
1306 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1308 bits<4> Rd;
1313 let Inst{15-12} = Rd;
1317 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1318 iir, opc, "\t$Rd, $Rn, $Rm",
1321 bits<4> Rd;
1327 let Inst{15-12} = Rd;
1331 def rsi : AsI1<opcod, (outs GPR:$Rd),
1333 iis, opc, "\t$Rd, $Rn, $shift",
1334 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1336 bits<4> Rd;
1341 let Inst{15-12} = Rd;
1347 def rsr : AsI1<opcod, (outs GPR:$Rd),
1349 iis, opc, "\t$Rd, $Rn, $shift",
1350 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1352 bits<4> Rd;
1357 let Inst{15-12} = Rd;
1374 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1376 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1379 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1381 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1385 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1388 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1392 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1395 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1407 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1409 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1412 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1415 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1419 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1422 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1511 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1512 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1513 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1515 bits<4> Rd;
1519 let Inst{15-12} = Rd;
1525 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1526 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1536 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1537 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1538 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1541 bits<4> Rd;
1546 let Inst{15-12} = Rd;
1553 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1554 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1563 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1567 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1568 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1569 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1572 bits<4> Rd;
1576 let Inst{15-12} = Rd;
1580 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1581 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1582 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1585 bits<4> Rd;
1592 let Inst{15-12} = Rd;
1595 def rsi : AsI1<opcod, (outs GPR:$Rd),
1597 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1598 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1601 bits<4> Rd;
1606 let Inst{15-12} = Rd;
1611 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1613 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1614 [(set GPRnopc:$Rd, CPSR,
1618 bits<4> Rd;
1623 let Inst{15-12} = Rd;
1634 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1637 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1638 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1639 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1642 bits<4> Rd;
1646 let Inst{15-12} = Rd;
1650 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1651 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1654 bits<4> Rd;
1660 let Inst{15-12} = Rd;
1663 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1664 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1665 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1668 bits<4> Rd;
1673 let Inst{15-12} = Rd;
1678 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1679 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1680 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1683 bits<4> Rd;
1688 let Inst{15-12} = Rd;
1892 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1893 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1894 bits<4> Rd;
1898 let Inst{15-12} = Rd;
2107 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2108 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2110 bits<4> Rd;
2118 let Inst{15-12} = Rd;
2123 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2126 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
3217 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3218 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3219 bits<4> Rd;
3226 let Inst{15-12} = Rd;
3231 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3232 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3233 bits<4> Rd;
3239 let Inst{15-12} = Rd;
3242 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3244 "mov", "\t$Rd, $src",
3245 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3247 bits<4> Rd;
3249 let Inst{15-12} = Rd;
3259 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3261 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3263 bits<4> Rd;
3265 let Inst{15-12} = Rd;
3274 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3275 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3277 bits<4> Rd;
3280 let Inst{15-12} = Rd;
3286 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3288 "movw", "\t$Rd, $imm",
3289 [(set GPR:$Rd, imm0_65535:$imm)]>,
3291 bits<4> Rd;
3293 let Inst{15-12} = Rd;
3301 def : InstAlias<"mov${p} $Rd, $imm",
3302 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3305 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3309 let Constraints = "$src = $Rd" in {
3310 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3313 "movt", "\t$Rd, $imm",
3314 [(set GPRnopc:$Rd,
3318 bits<4> Rd;
3320 let Inst{15-12} = Rd;
3328 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3338 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3339 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3403 def SBFX : I<(outs GPRnopc:$Rd),
3406 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3408 bits<4> Rd;
3415 let Inst{15-12} = Rd;
3420 def UBFX : I<(outs GPRnopc:$Rd),
3423 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3425 bits<4> Rd;
3432 let Inst{15-12} = Rd;
3517 string asm = "\t$Rd, $Rn, $Rm">
3518 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3521 bits<4> Rd;
3526 let Inst{15-12} = Rd;
3536 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3537 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3540 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3541 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3544 "\t$Rd, $Rm, $Rn">;
3547 "\t$Rd, $Rm, $Rn">;
3594 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3596 "\t$Rd, $Rn, $Rm", []>,
3598 bits<4> Rd;
3604 let Inst{19-16} = Rd;
3608 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3610 "\t$Rd, $Rn, $Rm, $Ra", []>,
3612 bits<4> Rd;
3618 let Inst{19-16} = Rd;
3626 def SSAT : AI<(outs GPRnopc:$Rd),
3628 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3629 bits<4> Rd;
3636 let Inst{15-12} = Rd;
3642 def SSAT16 : AI<(outs GPRnopc:$Rd),
3644 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3645 bits<4> Rd;
3650 let Inst{15-12} = Rd;
3655 def USAT : AI<(outs GPRnopc:$Rd),
3657 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3658 bits<4> Rd;
3664 let Inst{15-12} = Rd;
3671 def USAT16 : AI<(outs GPRnopc:$Rd),
3673 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3674 bits<4> Rd;
3679 let Inst{15-12} = Rd;
3710 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3712 "bfc", "\t$Rd, $imm", "$src = $Rd",
3713 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3715 bits<4> Rd;
3719 let Inst{15-12} = Rd;
3725 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3727 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3728 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3731 bits<4> Rd;
3736 let Inst{15-12} = Rd;
3742 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3743 "mvn", "\t$Rd, $Rm",
3744 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3745 bits<4> Rd;
3750 let Inst{15-12} = Rd;
3753 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3754 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3755 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3757 bits<4> Rd;
3761 let Inst{15-12} = Rd;
3766 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3767 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3768 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3770 bits<4> Rd;
3774 let Inst{15-12} = Rd;
3782 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3783 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3784 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3785 bits<4> Rd;
3789 let Inst{15-12} = Rd;
3802 bits<4> Rd;
3805 let Inst{19-16} = Rd;
3837 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3838 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3840 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3841 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3847 let Constraints = "@earlyclobber $Rd" in
3848 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3851 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3852 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3856 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3858 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3859 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3865 let Constraints = "@earlyclobber $Rd" in
3866 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3869 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3870 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3873 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3874 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3875 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3877 bits<4> Rd;
3881 let Inst{19-16} = Rd;
3958 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3959 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3960 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3965 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3966 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3971 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3973 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3974 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3977 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3979 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3982 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3984 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3987 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3989 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3993 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3994 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3995 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3999 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4000 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
4001 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
4005 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4006 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4007 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4011 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4012 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4013 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4017 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4018 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4022 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4023 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4031 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4033 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4034 [(set GPRnopc:$Rd, (add GPR:$Ra,
4039 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4041 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4042 [(set GPRnopc:$Rd,
4047 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4049 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4050 [(set GPRnopc:$Rd,
4055 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4057 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4058 [(set GPRnopc:$Rd,
4063 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4065 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4069 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4071 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4120 bits<4> Rd;
4122 let Inst{19-16} = Rd;
4128 bits<4> Rd;
4129 let Inst{19-16} = Rd;
4143 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4145 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4147 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4149 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4166 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4167 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4168 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4169 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4178 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4179 "sdiv", "\t$Rd, $Rn, $Rm",
4180 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4183 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4184 "udiv", "\t$Rd, $Rn, $Rm",
4185 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4192 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4193 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4194 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4197 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4198 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4199 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4203 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4204 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4205 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4209 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4210 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4211 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4221 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4222 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4223 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4231 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4233 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4234 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4248 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4250 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4251 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4280 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4281 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4282 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4284 bits<4> Rd;
4293 let Inst{15-12} = Rd;
4464 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4467 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4469 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4471 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4474 [(set GPR:$Rd,
4477 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4478 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4481 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4483 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4488 : ARMPseudoInst<(outs GPR:$Rd),
4491 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4493 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4497 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4500 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4502 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4507 : ARMPseudoInst<(outs GPR:$Rd),
4510 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4512 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4515 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4518 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4520 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4690 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4691 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4692 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4693 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4695 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4696 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4697 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4699 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4700 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4701 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4704 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4706 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4709 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4710 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4711 [(set GPR:$Rd,
4713 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4714 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4715 [(set GPR:$Rd,
4717 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4718 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4719 [(set GPR:$Rd,
4722 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4724 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
5155 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5156 "mrs", "\t$Rd, apsr", []> {
5157 bits<4> Rd;
5161 let Inst{15-12} = Rd;
5167 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5172 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5173 "mrs", "\t$Rd, spsr", []> {
5174 bits<4> Rd;
5178 let Inst{15-12} = Rd;
5186 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5187 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5190 bits<4> Rd;
5196 let Inst{15-12} = Rd;
5567 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5568 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5570 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5571 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5579 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5580 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5581 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5582 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5586 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5587 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5588 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5589 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5590 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5591 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5592 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5593 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5594 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5595 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5596 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5597 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5599 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5600 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5601 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5602 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5603 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5604 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5605 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5606 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5607 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5608 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5609 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5610 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5650 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5652 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5653 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5654 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5655 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5657 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5658 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
5663 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5664 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
5670 // Likewise, "add Rd, mod_imm_neg" -> sub
5671 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5672 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5673 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5674 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5676 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5677 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5678 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5679 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5686 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5687 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5688 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5690 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5691 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5693 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5694 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5696 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5697 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5700 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5701 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5702 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5703 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5704 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5706 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5707 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5709 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5710 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5712 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5713 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5718 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5719 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5728 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5729 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5731 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5732 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5754 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5756 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;