Lines Matching refs:Requires
1514 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1527 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1540 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1555 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1570 Requires<[IsARM]>,
1583 Requires<[IsARM]>,
1599 Requires<[IsARM]>,
1616 Requires<[IsARM]>,
1640 Requires<[IsARM]>,
1666 Requires<[IsARM]>,
1681 Requires<[IsARM]>,
1879 Requires<[IsARM, HasV6]> {
1885 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1886 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1887 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1888 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1889 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1890 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1893 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1909 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1918 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1921 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1934 []>, Requires<[IsARM]> {
1999 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
2000 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
2001 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
2004 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
2012 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
2049 Requires<[IsARM,UseNaClTrap]> {
2055 Requires<[IsARM,DontUseNaClTrap]> {
2139 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2146 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2162 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2170 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2187 Requires<[IsARM]>, Sched<[WriteBrL]> {
2197 Requires<[IsARM]>, Sched<[WriteBrL]> {
2207 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2216 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2226 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2231 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2237 Requires<[IsARM]>, Sched<[WriteBr]>;
2288 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2319 Requires<[IsARM]>, Sched<[WriteBr]>;
2324 Requires<[IsARM]>;
2329 []>, Requires<[IsARM, HasTrustZone]> {
2440 Requires<[IsARM, HasVirtualization]> {
2459 Requires<[IsARM, HasVirtualization]> {
2511 Requires<[IsARM, HasV5TE]>;
2778 Requires<[IsARM, HasV5TE]> {
3290 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3303 Requires<[IsARM]>;
3317 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3335 Requires<[IsARM, HasV6T2]>;
3340 Requires<[IsARM]>, Sched<[WriteALU]>;
3348 Sched<[WriteALU]>, Requires<[IsARM]>;
3351 Sched<[WriteALU]>, Requires<[IsARM]>;
3407 Requires<[IsARM, HasV6T2]> {
3424 Requires<[IsARM, HasV6T2]> {
3492 Requires<[IsARM, HasV6T2]>;
3495 Requires<[IsARM, HasV6T2]>;
3504 Requires<[IsARM, HasV6T2]>;
3597 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3611 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3714 Requires<[IsARM, HasV6T2]> {
3730 Requires<[IsARM, HasV6T2]> {
3842 Requires<[IsARM, HasV6]> {
3853 Requires<[IsARM, NoV6, UseMulOps]>;
3860 Requires<[IsARM, HasV6, UseMulOps]> {
3871 Requires<[IsARM, NoV6]>;
3876 Requires<[IsARM, HasV6T2, UseMulOps]> {
3893 Requires<[IsARM, HasV6]>;
3898 Requires<[IsARM, HasV6]>;
3905 Requires<[IsARM, NoV6]>;
3911 Requires<[IsARM, NoV6]>;
3919 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3923 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3928 Requires<[IsARM, HasV6]> {
3946 Requires<[IsARM, NoV6]>;
3952 Requires<[IsARM, NoV6]>;
3961 Requires<[IsARM, HasV6]> {
3967 Requires<[IsARM, HasV6]> {
3975 Requires<[IsARM, HasV6, UseMulOps]>;
3980 Requires<[IsARM, HasV6]>;
3985 Requires<[IsARM, HasV6, UseMulOps]>;
3990 Requires<[IsARM, HasV6]>;
3997 Requires<[IsARM, HasV5TE]>;
4003 Requires<[IsARM, HasV5TE]>;
4009 Requires<[IsARM, HasV5TE]>;
4015 Requires<[IsARM, HasV5TE]>;
4020 Requires<[IsARM, HasV5TE]>;
4025 Requires<[IsARM, HasV5TE]>;
4037 Requires<[IsARM, HasV5TE, UseMulOps]>;
4045 Requires<[IsARM, HasV5TE, UseMulOps]>;
4053 Requires<[IsARM, HasV5TE, UseMulOps]>;
4061 Requires<[IsARM, HasV5TE, UseMulOps]>;
4067 Requires<[IsARM, HasV5TE, UseMulOps]>;
4073 Requires<[IsARM, HasV5TE, UseMulOps]>;
4084 Requires<[IsARM, HasV5TE]>;
4089 Requires<[IsARM, HasV5TE]>;
4094 Requires<[IsARM, HasV5TE]>;
4099 Requires<[IsARM, HasV5TE]>;
4104 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4181 Requires<[IsARM, HasDivideInARM]>;
4186 Requires<[IsARM, HasDivideInARM]>;
4194 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4200 Requires<[IsARM, HasV6T2]>,
4205 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4212 Requires<[IsARM, HasV6]>,
4224 Requires<[IsARM, HasV6]>,
4237 Requires<[IsARM, HasV6]>,
4254 Requires<[IsARM, HasV6]>,
4283 Requires<[IsARM, HasV8, HasCRC]> {
4316 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4493 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4512 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4553 Requires<[IsARM, HasDB]> {
4561 Requires<[IsARM, HasDB]> {
4570 Requires<[IsARM, HasDB]> {
4731 Requires<[IsARM, HasV7]> {
4778 Requires<[PreV8]>;
4781 Requires<[PreV8]>;
4793 Requires<[PreV8]> {
4815 Requires<[PreV8]> {
4993 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4994 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4995 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4996 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
5074 Requires<[PreV8]>;
5082 Requires<[PreV8]>;
5125 Requires<[PreV8]> {
5168 Requires<[IsARM]>;
5188 Requires<[IsARM, HasVirtualization]> {
5240 Requires<[IsARM, HasVirtualization]> {
5312 Requires<[IsARM, HasVFP2]>;
5321 Requires<[IsARM, NoVFP]>;
5330 Requires<[IsARM]>;
5354 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5365 Requires<[IsARM]>;
5369 Requires<[IsARM, DontUseMovt]>;
5379 Requires<[IsARM, UseMovt]>;
5385 Requires<[IsARM, DontUseMovt]>;
5392 Requires<[IsARM, DontUseMovt]>;
5398 Requires<[IsARM, UseMovt]>;
5404 Requires<[IsARM, UseMovt]>;
5477 Requires<[IsARM, HasV6]>;
5550 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5551 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5552 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5569 Requires<[IsARM, HasV6]>;
5572 Requires<[IsARM, HasV6]>;
5723 Requires<[IsARM, NoV6]>;
5730 Requires<[IsARM, NoV6]>;
5734 Requires<[IsARM, NoV6]>;
5737 Requires<[IsARM, NoV6]>;
5740 Requires<[IsARM, NoV6]>;
5743 Requires<[IsARM, NoV6]>;
5746 Requires<[IsARM, NoV6]>;