Lines Matching refs:Rt
1704 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1705 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1706 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1707 bits<4> Rt;
1711 let Inst{15-12} = Rt;
1714 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1715 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1716 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1717 bits<4> Rt;
1722 let Inst{15-12} = Rt;
1734 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1736 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1737 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1738 bits<4> Rt;
1742 let Inst{15-12} = Rt;
1745 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1747 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1748 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1749 bits<4> Rt;
1754 let Inst{15-12} = Rt;
1767 (ins GPR:$Rt, addrmode_imm12:$addr),
1768 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1769 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1770 bits<4> Rt;
1774 let Inst{15-12} = Rt;
1777 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1778 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1779 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1780 bits<4> Rt;
1785 let Inst{15-12} = Rt;
1796 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1797 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1798 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1799 bits<4> Rt;
1803 let Inst{15-12} = Rt;
1807 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1808 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1809 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1810 bits<4> Rt;
1815 let Inst{15-12} = Rt;
1968 bits<4> Rt;
2071 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2073 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2075 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2077 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2079 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2081 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2083 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2085 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2482 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2483 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2485 bits<4> Rt;
2489 let Inst{15-12} = Rt;
2494 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2495 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2496 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2499 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2500 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2501 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2503 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2504 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2505 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2509 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2510 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2514 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2515 NoItinerary, "lda", "\t$Rt, $addr", []>;
2516 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2517 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2518 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2519 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2524 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2526 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2535 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2537 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2547 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2550 opc, "\t$Rt, $addr, $offset",
2565 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2568 opc, "\t$Rt, $addr, $offset",
2592 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2595 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2604 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2607 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2625 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2628 "ldrd", "\t$Rt, $Rt2, $addr!",
2638 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2641 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2657 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2660 "ldrt", "\t$Rt, $addr, $offset",
2677 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2680 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2693 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2696 "ldrbt", "\t$Rt, $addr, $offset",
2713 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2716 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2730 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2733 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2740 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2743 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2760 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2761 (outs GPR:$Rt)>;
2764 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2765 (outs GPR:$Rt)>;
2770 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2771 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2772 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2776 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2777 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2787 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2789 opc, "\t$Rt, $addr!",
2800 (ins GPR:$Rt, ldst_so_reg:$addr),
2802 opc, "\t$Rt, $addr!",
2813 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2815 opc, "\t$Rt, $addr, $offset",
2831 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2833 opc, "\t$Rt, $addr, $offset",
2855 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2857 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2859 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2861 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2863 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2865 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2867 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2869 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2880 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2883 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2885 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2888 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2890 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2893 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2895 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2898 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2900 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2903 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2909 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2911 "strh", "\t$Rt, $addr!",
2923 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2925 "strh", "\t$Rt, $addr, $offset",
2927 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2942 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2944 "strd", "\t$Rt, $Rt2, $addr!",
2956 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2959 "strd", "\t$Rt, $Rt2, $addr, $offset",
2975 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2977 "strbt", "\t$Rt, $addr, $offset",
2995 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2997 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3011 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
3012 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3016 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3018 "strt", "\t$Rt, $addr, $offset",
3036 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3038 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3053 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3054 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3058 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3060 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3068 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3070 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3082 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3083 NoItinerary, "stl", "\t$Rt, $addr", []>;
3084 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3085 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3086 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3087 NoItinerary, "stlh", "\t$Rt, $addr", []>;
4659 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4660 NoItinerary, "ldrexb", "\t$Rt, $addr",
4661 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4662 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4663 NoItinerary, "ldrexh", "\t$Rt, $addr",
4664 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4665 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4666 NoItinerary, "ldrex", "\t$Rt, $addr",
4667 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4669 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4670 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4674 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4675 NoItinerary, "ldaexb", "\t$Rt, $addr",
4676 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4677 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4678 NoItinerary, "ldaexh", "\t$Rt, $addr",
4679 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4680 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4681 NoItinerary, "ldaex", "\t$Rt, $addr",
4682 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4684 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4685 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4691 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4692 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4693 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4695 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4696 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4697 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4699 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4700 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4701 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4705 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4706 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4709 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4710 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4712 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4713 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4714 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4716 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4717 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4718 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4720 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4723 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4724 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4735 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4736 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4737 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4738 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4740 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4741 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4742 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4743 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4776 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4779 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
5005 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
5009 bits<4> Rt;
5016 let Inst{15-12} = Rt;
5026 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5028 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5031 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
5032 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5035 (outs GPRwithAPSR:$Rt),
5038 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5039 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5048 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5053 bits<4> Rt;
5060 let Inst{15-12} = Rt;
5070 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5072 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5075 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5076 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5079 (outs GPRwithAPSR:$Rt),
5083 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5084 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5093 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
5099 bits<4> Rt;
5105 let Inst{15-12} = Rt;
5113 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5115 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5118 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5123 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5124 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5130 bits<4> Rt;
5136 let Inst{15-12} = Rt;
5146 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,