1494                           unsigned BaseReg, bool BaseKill, bool BaseUndef,  in InsertLDR_STR()  argument
1502       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1508       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1521   unsigned BaseReg = BaseOp.getReg();  in FixInvalidRegPairOp()  local
1529   bool Errata602117 = EvenReg == BaseReg &&  in FixInvalidRegPairOp()
1562         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1569         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1592         (TRI->regsOverlap(EvenReg, BaseReg))) {  in FixInvalidRegPairOp()
1593       assert(!TRI->regsOverlap(OddReg, BaseReg));  in FixInvalidRegPairOp()
1596                     BaseReg, false, BaseUndef, false, OffUndef,  in FixInvalidRegPairOp()
1600                     BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,  in FixInvalidRegPairOp()
1611       if (EvenReg == BaseReg)  in FixInvalidRegPairOp()
1615                     BaseReg, false, BaseUndef, false, OffUndef,  in FixInvalidRegPairOp()
1619                     BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,  in FixInvalidRegPairOp()
1912                           unsigned &OddReg, unsigned &BaseReg,
2011                                           unsigned &BaseReg, int &Offset,  in CanFormLdStDWord()  argument
2075   BaseReg = Op0->getOperand(1).getReg();  in CanFormLdStDWord()
2170         unsigned BaseReg = 0, PredReg = 0;  in RescheduleOps()  local
2177                                              FirstReg, SecondReg, BaseReg,  in RescheduleOps()
2192               .addReg(BaseReg);  in RescheduleOps()
2206               .addReg(BaseReg);  in RescheduleOps()