Lines Matching refs:Inst
192 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
194 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
332 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
333 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
335 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
336 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
377 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1673 void addExpr(MCInst &Inst, const MCExpr *Expr) const { in addExpr() argument
1676 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
1678 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
1680 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
1683 void addCondCodeOperands(MCInst &Inst, unsigned N) const { in addCondCodeOperands() argument
1685 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
1687 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
1690 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { in addCoprocNumOperands() argument
1692 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocNumOperands()
1695 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { in addCoprocRegOperands() argument
1697 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocRegOperands()
1700 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { in addCoprocOptionOperands() argument
1702 Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); in addCoprocOptionOperands()
1705 void addITMaskOperands(MCInst &Inst, unsigned N) const { in addITMaskOperands() argument
1707 Inst.addOperand(MCOperand::createImm(ITMask.Mask)); in addITMaskOperands()
1710 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { in addITCondCodeOperands() argument
1712 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
1715 void addCCOutOperands(MCInst &Inst, unsigned N) const { in addCCOutOperands() argument
1717 Inst.addOperand(MCOperand::createReg(getReg())); in addCCOutOperands()
1720 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() argument
1722 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
1725 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { in addRegShiftedRegOperands() argument
1729 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); in addRegShiftedRegOperands()
1730 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
1731 Inst.addOperand(MCOperand::createImm( in addRegShiftedRegOperands()
1735 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { in addRegShiftedImmOperands() argument
1739 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); in addRegShiftedImmOperands()
1742 Inst.addOperand(MCOperand::createImm( in addRegShiftedImmOperands()
1746 void addShifterImmOperands(MCInst &Inst, unsigned N) const { in addShifterImmOperands() argument
1748 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) | in addShifterImmOperands()
1752 void addRegListOperands(MCInst &Inst, unsigned N) const { in addRegListOperands() argument
1757 Inst.addOperand(MCOperand::createReg(*I)); in addRegListOperands()
1760 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { in addDPRRegListOperands() argument
1761 addRegListOperands(Inst, N); in addDPRRegListOperands()
1764 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { in addSPRRegListOperands() argument
1765 addRegListOperands(Inst, N); in addSPRRegListOperands()
1768 void addRotImmOperands(MCInst &Inst, unsigned N) const { in addRotImmOperands() argument
1771 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3)); in addRotImmOperands()
1774 void addModImmOperands(MCInst &Inst, unsigned N) const { in addModImmOperands() argument
1779 return addImmOperands(Inst, N); in addModImmOperands()
1781 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7))); in addModImmOperands()
1784 void addModImmNotOperands(MCInst &Inst, unsigned N) const { in addModImmNotOperands() argument
1788 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNotOperands()
1791 void addModImmNegOperands(MCInst &Inst, unsigned N) const { in addModImmNegOperands() argument
1795 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNegOperands()
1798 void addBitfieldOperands(MCInst &Inst, unsigned N) const { in addBitfieldOperands() argument
1806 Inst.addOperand(MCOperand::createImm(Mask)); in addBitfieldOperands()
1809 void addImmOperands(MCInst &Inst, unsigned N) const { in addImmOperands() argument
1811 addExpr(Inst, getImm()); in addImmOperands()
1814 void addFBits16Operands(MCInst &Inst, unsigned N) const { in addFBits16Operands() argument
1817 Inst.addOperand(MCOperand::createImm(16 - CE->getValue())); in addFBits16Operands()
1820 void addFBits32Operands(MCInst &Inst, unsigned N) const { in addFBits32Operands() argument
1823 Inst.addOperand(MCOperand::createImm(32 - CE->getValue())); in addFBits32Operands()
1826 void addFPImmOperands(MCInst &Inst, unsigned N) const { in addFPImmOperands() argument
1830 Inst.addOperand(MCOperand::createImm(Val)); in addFPImmOperands()
1833 void addImm8s4Operands(MCInst &Inst, unsigned N) const { in addImm8s4Operands() argument
1838 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addImm8s4Operands()
1841 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { in addImm0_1020s4Operands() argument
1846 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); in addImm0_1020s4Operands()
1849 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { in addImm0_508s4NegOperands() argument
1854 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4))); in addImm0_508s4NegOperands()
1857 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { in addImm0_508s4Operands() argument
1862 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); in addImm0_508s4Operands()
1865 void addImm1_16Operands(MCInst &Inst, unsigned N) const { in addImm1_16Operands() argument
1870 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); in addImm1_16Operands()
1873 void addImm1_32Operands(MCInst &Inst, unsigned N) const { in addImm1_32Operands() argument
1878 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); in addImm1_32Operands()
1881 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { in addImmThumbSROperands() argument
1887 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm))); in addImmThumbSROperands()
1890 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { in addPKHASRImmOperands() argument
1896 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val)); in addPKHASRImmOperands()
1899 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { in addT2SOImmNotOperands() argument
1904 Inst.addOperand(MCOperand::createImm(~CE->getValue())); in addT2SOImmNotOperands()
1907 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { in addT2SOImmNegOperands() argument
1912 Inst.addOperand(MCOperand::createImm(-CE->getValue())); in addT2SOImmNegOperands()
1915 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { in addImm0_4095NegOperands() argument
1920 Inst.addOperand(MCOperand::createImm(-CE->getValue())); in addImm0_4095NegOperands()
1923 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { in addUnsignedOffset_b8s2Operands() argument
1925 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2)); in addUnsignedOffset_b8s2Operands()
1931 Inst.addOperand(MCOperand::createExpr(SR)); in addUnsignedOffset_b8s2Operands()
1934 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { in addThumbMemPCOperands() argument
1939 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addThumbMemPCOperands()
1945 Inst.addOperand(MCOperand::createExpr(SR)); in addThumbMemPCOperands()
1951 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue())); in addThumbMemPCOperands()
1954 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { in addMemBarrierOptOperands() argument
1956 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt()))); in addMemBarrierOptOperands()
1959 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { in addInstSyncBarrierOptOperands() argument
1961 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt()))); in addInstSyncBarrierOptOperands()
1964 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { in addMemNoOffsetOperands() argument
1966 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemNoOffsetOperands()
1969 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { in addMemPCRelImm12Operands() argument
1972 Inst.addOperand(MCOperand::createImm(Imm)); in addMemPCRelImm12Operands()
1975 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { in addAdrLabelOperands() argument
1982 Inst.addOperand(MCOperand::createExpr(getImm())); in addAdrLabelOperands()
1988 Inst.addOperand(MCOperand::createImm(Val)); in addAdrLabelOperands()
1991 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { in addAlignedMemoryOperands() argument
1993 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAlignedMemoryOperands()
1994 Inst.addOperand(MCOperand::createImm(Memory.Alignment)); in addAlignedMemoryOperands()
1997 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { in addDupAlignedMemoryNoneOperands() argument
1998 addAlignedMemoryOperands(Inst, N); in addDupAlignedMemoryNoneOperands()
2001 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { in addAlignedMemoryNoneOperands() argument
2002 addAlignedMemoryOperands(Inst, N); in addAlignedMemoryNoneOperands()
2005 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const { in addAlignedMemory16Operands() argument
2006 addAlignedMemoryOperands(Inst, N); in addAlignedMemory16Operands()
2009 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const { in addDupAlignedMemory16Operands() argument
2010 addAlignedMemoryOperands(Inst, N); in addDupAlignedMemory16Operands()
2013 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const { in addAlignedMemory32Operands() argument
2014 addAlignedMemoryOperands(Inst, N); in addAlignedMemory32Operands()
2017 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const { in addDupAlignedMemory32Operands() argument
2018 addAlignedMemoryOperands(Inst, N); in addDupAlignedMemory32Operands()
2021 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const { in addAlignedMemory64Operands() argument
2022 addAlignedMemoryOperands(Inst, N); in addAlignedMemory64Operands()
2025 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const { in addDupAlignedMemory64Operands() argument
2026 addAlignedMemoryOperands(Inst, N); in addDupAlignedMemory64Operands()
2029 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { in addAlignedMemory64or128Operands() argument
2030 addAlignedMemoryOperands(Inst, N); in addAlignedMemory64or128Operands()
2033 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { in addDupAlignedMemory64or128Operands() argument
2034 addAlignedMemoryOperands(Inst, N); in addDupAlignedMemory64or128Operands()
2037 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const { in addAlignedMemory64or128or256Operands() argument
2038 addAlignedMemoryOperands(Inst, N); in addAlignedMemory64or128or256Operands()
2041 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { in addAddrMode2Operands() argument
2056 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAddrMode2Operands()
2057 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); in addAddrMode2Operands()
2058 Inst.addOperand(MCOperand::createImm(Val)); in addAddrMode2Operands()
2061 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { in addAM2OffsetImmOperands() argument
2071 Inst.addOperand(MCOperand::createReg(0)); in addAM2OffsetImmOperands()
2072 Inst.addOperand(MCOperand::createImm(Val)); in addAM2OffsetImmOperands()
2075 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { in addAddrMode3Operands() argument
2081 Inst.addOperand(MCOperand::createExpr(getImm())); in addAddrMode3Operands()
2082 Inst.addOperand(MCOperand::createReg(0)); in addAddrMode3Operands()
2083 Inst.addOperand(MCOperand::createImm(0)); in addAddrMode3Operands()
2099 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAddrMode3Operands()
2100 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); in addAddrMode3Operands()
2101 Inst.addOperand(MCOperand::createImm(Val)); in addAddrMode3Operands()
2104 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { in addAM3OffsetOperands() argument
2109 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); in addAM3OffsetOperands()
2110 Inst.addOperand(MCOperand::createImm(Val)); in addAM3OffsetOperands()
2122 Inst.addOperand(MCOperand::createReg(0)); in addAM3OffsetOperands()
2123 Inst.addOperand(MCOperand::createImm(Val)); in addAM3OffsetOperands()
2126 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { in addAddrMode5Operands() argument
2132 Inst.addOperand(MCOperand::createExpr(getImm())); in addAddrMode5Operands()
2133 Inst.addOperand(MCOperand::createImm(0)); in addAddrMode5Operands()
2144 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAddrMode5Operands()
2145 Inst.addOperand(MCOperand::createImm(Val)); in addAddrMode5Operands()
2148 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { in addMemImm8s4OffsetOperands() argument
2154 Inst.addOperand(MCOperand::createExpr(getImm())); in addMemImm8s4OffsetOperands()
2155 Inst.addOperand(MCOperand::createImm(0)); in addMemImm8s4OffsetOperands()
2160 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemImm8s4OffsetOperands()
2161 Inst.addOperand(MCOperand::createImm(Val)); in addMemImm8s4OffsetOperands()
2164 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { in addMemImm0_1020s4OffsetOperands() argument
2168 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemImm0_1020s4OffsetOperands()
2169 Inst.addOperand(MCOperand::createImm(Val)); in addMemImm0_1020s4OffsetOperands()
2172 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { in addMemImm8OffsetOperands() argument
2175 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemImm8OffsetOperands()
2176 Inst.addOperand(MCOperand::createImm(Val)); in addMemImm8OffsetOperands()
2179 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { in addMemPosImm8OffsetOperands() argument
2180 addMemImm8OffsetOperands(Inst, N); in addMemPosImm8OffsetOperands()
2183 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { in addMemNegImm8OffsetOperands() argument
2184 addMemImm8OffsetOperands(Inst, N); in addMemNegImm8OffsetOperands()
2187 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { in addMemUImm12OffsetOperands() argument
2191 addExpr(Inst, getImm()); in addMemUImm12OffsetOperands()
2192 Inst.addOperand(MCOperand::createImm(0)); in addMemUImm12OffsetOperands()
2198 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemUImm12OffsetOperands()
2199 Inst.addOperand(MCOperand::createImm(Val)); in addMemUImm12OffsetOperands()
2202 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { in addMemImm12OffsetOperands() argument
2206 addExpr(Inst, getImm()); in addMemImm12OffsetOperands()
2207 Inst.addOperand(MCOperand::createImm(0)); in addMemImm12OffsetOperands()
2213 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemImm12OffsetOperands()
2214 Inst.addOperand(MCOperand::createImm(Val)); in addMemImm12OffsetOperands()
2217 void addMemTBBOperands(MCInst &Inst, unsigned N) const { in addMemTBBOperands() argument
2219 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemTBBOperands()
2220 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); in addMemTBBOperands()
2223 void addMemTBHOperands(MCInst &Inst, unsigned N) const { in addMemTBHOperands() argument
2225 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemTBHOperands()
2226 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); in addMemTBHOperands()
2229 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { in addMemRegOffsetOperands() argument
2234 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemRegOffsetOperands()
2235 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); in addMemRegOffsetOperands()
2236 Inst.addOperand(MCOperand::createImm(Val)); in addMemRegOffsetOperands()
2239 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { in addT2MemRegOffsetOperands() argument
2241 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addT2MemRegOffsetOperands()
2242 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); in addT2MemRegOffsetOperands()
2243 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm)); in addT2MemRegOffsetOperands()
2246 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { in addMemThumbRROperands() argument
2248 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemThumbRROperands()
2249 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); in addMemThumbRROperands()
2252 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { in addMemThumbRIs4Operands() argument
2255 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemThumbRIs4Operands()
2256 Inst.addOperand(MCOperand::createImm(Val)); in addMemThumbRIs4Operands()
2259 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { in addMemThumbRIs2Operands() argument
2262 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemThumbRIs2Operands()
2263 Inst.addOperand(MCOperand::createImm(Val)); in addMemThumbRIs2Operands()
2266 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { in addMemThumbRIs1Operands() argument
2269 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemThumbRIs1Operands()
2270 Inst.addOperand(MCOperand::createImm(Val)); in addMemThumbRIs1Operands()
2273 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { in addMemThumbSPIOperands() argument
2276 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemThumbSPIOperands()
2277 Inst.addOperand(MCOperand::createImm(Val)); in addMemThumbSPIOperands()
2280 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { in addPostIdxImm8Operands() argument
2288 Inst.addOperand(MCOperand::createImm(Imm)); in addPostIdxImm8Operands()
2291 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { in addPostIdxImm8s4Operands() argument
2300 Inst.addOperand(MCOperand::createImm(Imm)); in addPostIdxImm8s4Operands()
2303 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { in addPostIdxRegOperands() argument
2305 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); in addPostIdxRegOperands()
2306 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
2309 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { in addPostIdxRegShiftedOperands() argument
2311 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); in addPostIdxRegShiftedOperands()
2317 Inst.addOperand(MCOperand::createImm(Imm)); in addPostIdxRegShiftedOperands()
2320 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { in addMSRMaskOperands() argument
2322 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask()))); in addMSRMaskOperands()
2325 void addBankedRegOperands(MCInst &Inst, unsigned N) const { in addBankedRegOperands() argument
2327 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg()))); in addBankedRegOperands()
2330 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { in addProcIFlagsOperands() argument
2332 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags()))); in addProcIFlagsOperands()
2335 void addVecListOperands(MCInst &Inst, unsigned N) const { in addVecListOperands() argument
2337 Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); in addVecListOperands()
2340 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { in addVecListIndexedOperands() argument
2342 Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); in addVecListIndexedOperands()
2343 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex)); in addVecListIndexedOperands()
2346 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { in addVectorIndex8Operands() argument
2348 Inst.addOperand(MCOperand::createImm(getVectorIndex())); in addVectorIndex8Operands()
2351 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { in addVectorIndex16Operands() argument
2353 Inst.addOperand(MCOperand::createImm(getVectorIndex())); in addVectorIndex16Operands()
2356 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { in addVectorIndex32Operands() argument
2358 Inst.addOperand(MCOperand::createImm(getVectorIndex())); in addVectorIndex32Operands()
2361 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { in addNEONi8splatOperands() argument
2366 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00)); in addNEONi8splatOperands()
2369 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { in addNEONi16splatOperands() argument
2375 Inst.addOperand(MCOperand::createImm(Value)); in addNEONi16splatOperands()
2378 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const { in addNEONi16splatNotOperands() argument
2384 Inst.addOperand(MCOperand::createImm(Value)); in addNEONi16splatNotOperands()
2387 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { in addNEONi32splatOperands() argument
2393 Inst.addOperand(MCOperand::createImm(Value)); in addNEONi32splatOperands()
2396 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const { in addNEONi32splatNotOperands() argument
2402 Inst.addOperand(MCOperand::createImm(Value)); in addNEONi32splatNotOperands()
2405 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const { in addNEONinvByteReplicateOperands() argument
2410 assert((Inst.getOpcode() == ARM::VMOVv8i8 || in addNEONinvByteReplicateOperands()
2411 Inst.getOpcode() == ARM::VMOVv16i8) && in addNEONinvByteReplicateOperands()
2416 Inst.addOperand(MCOperand::createImm(B)); in addNEONinvByteReplicateOperands()
2418 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { in addNEONi32vmovOperands() argument
2429 Inst.addOperand(MCOperand::createImm(Value)); in addNEONi32vmovOperands()
2432 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const { in addNEONvmovByteReplicateOperands() argument
2437 assert((Inst.getOpcode() == ARM::VMOVv8i8 || in addNEONvmovByteReplicateOperands()
2438 Inst.getOpcode() == ARM::VMOVv16i8) && in addNEONvmovByteReplicateOperands()
2443 Inst.addOperand(MCOperand::createImm(B)); in addNEONvmovByteReplicateOperands()
2445 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { in addNEONi32vmovNegOperands() argument
2456 Inst.addOperand(MCOperand::createImm(Value)); in addNEONi32vmovNegOperands()
2459 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { in addNEONi64splatOperands() argument
2468 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00)); in addNEONi64splatOperands()
4618 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst, in cvtThumbMultiply() argument
4620 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); in cvtThumbMultiply()
4621 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); in cvtThumbMultiply()
4629 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
4630 Inst.addOperand(Inst.getOperand(0)); in cvtThumbMultiply()
4631 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); in cvtThumbMultiply()
4634 void ARMAsmParser::cvtThumbBranches(MCInst &Inst, in cvtThumbBranches() argument
4637 switch(Inst.getOpcode()) { in cvtThumbBranches()
4651 switch(Inst.getOpcode()) { in cvtThumbBranches()
4652 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; in cvtThumbBranches()
4653 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; in cvtThumbBranches()
4659 switch(Inst.getOpcode()) { in cvtThumbBranches()
4662 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); in cvtThumbBranches()
4666 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); in cvtThumbBranches()
4672 switch(Inst.getOpcode()) { in cvtThumbBranches()
4677 Inst.setOpcode(ARM::t2B); in cvtThumbBranches()
4684 Inst.setOpcode(ARM::t2Bcc); in cvtThumbBranches()
4688 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); in cvtThumbBranches()
4689 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); in cvtThumbBranches()
5643 static bool RequiresVFPRegListValidation(StringRef Inst, in RequiresVFPRegListValidation() argument
5646 if (Inst.size() < 7) in RequiresVFPRegListValidation()
5649 if (Inst.startswith("fldm") || Inst.startswith("fstm")) { in RequiresVFPRegListValidation()
5650 StringRef AddressingMode = Inst.substr(4, 2); in RequiresVFPRegListValidation()
5653 AcceptSinglePrecisionOnly = Inst[6] == 's'; in RequiresVFPRegListValidation()
5654 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x'; in RequiresVFPRegListValidation()
5962 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo, in checkLowRegisterList() argument
5966 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { in checkLowRegisterList()
5967 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList()
5979 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) { in listContainsReg() argument
5980 for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) { in listContainsReg()
5981 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg()
5990 static bool instIsBreakpoint(const MCInst &Inst) { in instIsBreakpoint() argument
5991 return Inst.getOpcode() == ARM::tBKPT || in instIsBreakpoint()
5992 Inst.getOpcode() == ARM::BKPT || in instIsBreakpoint()
5993 Inst.getOpcode() == ARM::tHLT || in instIsBreakpoint()
5994 Inst.getOpcode() == ARM::HLT; in instIsBreakpoint()
5998 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst, in validatetLDMRegList() argument
6004 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); in validatetLDMRegList()
6005 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR); in validatetLDMRegList()
6006 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); in validatetLDMRegList()
6021 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst, in validatetSTMRegList() argument
6027 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); in validatetSTMRegList()
6028 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); in validatetSTMRegList()
6043 bool ARMAsmParser::validateInstruction(MCInst &Inst, in validateInstruction() argument
6045 const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); in validateInstruction()
6051 if (inITBlock() && !instIsBreakpoint(Inst)) { in validateInstruction()
6060 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); in validateInstruction()
6076 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != in validateInstruction()
6077 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && in validateInstruction()
6078 Inst.getOpcode() != ARM::t2Bcc) in validateInstruction()
6081 const unsigned Opcode = Inst.getOpcode(); in validateInstruction()
6086 const unsigned RtReg = Inst.getOperand(0).getReg(); in validateInstruction()
6100 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
6106 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); in validateInstruction()
6121 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction()
6122 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
6129 const unsigned RmReg = Inst.getOperand(0).getReg(); in validateInstruction()
6138 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction()
6139 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
6148 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
6149 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction()
6166 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
6167 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction()
6189 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction()
6190 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction()
6200 unsigned LSB = Inst.getOperand(2).getImm(); in validateInstruction()
6201 unsigned Widthm1 = Inst.getOperand(3).getImm(); in validateInstruction()
6215 unsigned Rn = Inst.getOperand(0).getReg(); in validateInstruction()
6220 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo()) in validateInstruction()
6234 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
6246 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) in validateInstruction()
6252 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
6257 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
6264 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) in validateInstruction()
6269 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
6272 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
6281 if (!listContainsReg(Inst, 3, ARM::PC)) in validateInstruction()
6315 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && in validateInstruction()
6319 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) in validateInstruction()
6325 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && in validateInstruction()
6329 if (validatetSTMRegList(Inst, Operands, 2)) in validateInstruction()
6335 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(), in validateInstruction()
6348 if (validatetSTMRegList(Inst, Operands, 4)) in validateInstruction()
6356 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { in validateInstruction()
6669 bool ARMAsmParser::processInstruction(MCInst &Inst, in processInstruction() argument
6672 switch (Inst.getOpcode()) { in processInstruction()
6677 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM in processInstruction()
6681 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
6682 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
6683 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
6686 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
6687 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
6688 Inst = TmpInst; in processInstruction()
6695 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM in processInstruction()
6699 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
6700 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
6701 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
6704 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
6705 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
6706 Inst = TmpInst; in processInstruction()
6711 if (Inst.getOperand(1).getReg() != ARM::PC || in processInstruction()
6712 Inst.getOperand(5).getReg() != 0 || in processInstruction()
6713 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) in processInstruction()
6717 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
6718 if (Inst.getOperand(2).isImm()) { in processInstruction()
6721 unsigned Enc = Inst.getOperand(2).getImm(); in processInstruction()
6730 const MCExpr *OpExpr = Inst.getOperand(2).getExpr(); in processInstruction()
6741 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
6742 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
6743 Inst = TmpInst; in processInstruction()
6749 if (Inst.getOperand(1).getImm() > 0 && in processInstruction()
6750 Inst.getOperand(1).getImm() <= 0xff && in processInstruction()
6753 Inst.setOpcode(ARM::tLDRpci); in processInstruction()
6755 Inst.setOpcode(ARM::t2LDRpci); in processInstruction()
6758 Inst.setOpcode(ARM::t2LDRBpci); in processInstruction()
6761 Inst.setOpcode(ARM::t2LDRHpci); in processInstruction()
6764 Inst.setOpcode(ARM::t2LDRSBpci); in processInstruction()
6767 Inst.setOpcode(ARM::t2LDRSHpci); in processInstruction()
6777 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6778 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6779 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6780 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6781 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
6782 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6783 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6784 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
6785 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
6786 Inst = TmpInst; in processInstruction()
6799 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6800 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6801 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6802 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6803 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
6804 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6805 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6807 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6808 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
6809 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
6810 Inst = TmpInst; in processInstruction()
6823 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6824 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6825 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6826 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6827 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
6828 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6829 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6831 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6833 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6834 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
6835 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
6836 Inst = TmpInst; in processInstruction()
6849 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6850 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6851 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6852 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6853 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
6854 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6855 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6857 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6859 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6861 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6862 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
6863 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
6864 Inst = TmpInst; in processInstruction()
6875 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6876 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6877 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6878 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6880 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6881 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6882 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6883 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6884 Inst = TmpInst; in processInstruction()
6897 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6898 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6899 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6900 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6902 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6903 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6905 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6906 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6907 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6908 Inst = TmpInst; in processInstruction()
6921 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6922 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6923 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6924 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6926 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6927 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6929 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6931 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6932 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6933 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6934 Inst = TmpInst; in processInstruction()
6947 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6948 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
6949 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6950 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6952 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6953 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6955 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6957 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6959 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6960 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6961 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6962 Inst = TmpInst; in processInstruction()
6973 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6974 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6975 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6976 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6977 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
6978 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
6979 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
6980 Inst = TmpInst; in processInstruction()
6993 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
6994 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
6995 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
6996 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
6997 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
6999 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7000 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7001 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7002 Inst = TmpInst; in processInstruction()
7015 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7016 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7017 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7018 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7019 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7021 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7023 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7024 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7025 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7026 Inst = TmpInst; in processInstruction()
7039 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7040 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7041 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7042 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7043 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7045 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7047 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7049 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7050 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7051 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7052 Inst = TmpInst; in processInstruction()
7064 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7065 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7066 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
7067 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7068 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7069 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
7070 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7071 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7072 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
7073 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
7074 Inst = TmpInst; in processInstruction()
7087 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7088 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7089 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7091 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
7092 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7093 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7094 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
7095 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7096 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7098 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7099 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
7100 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
7101 Inst = TmpInst; in processInstruction()
7114 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7115 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7116 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7118 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7120 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
7121 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7122 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7123 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
7124 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7125 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7127 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7129 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7130 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
7131 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
7132 Inst = TmpInst; in processInstruction()
7145 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7146 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7147 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7149 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7151 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7153 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
7154 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7155 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7156 TmpInst.addOperand(Inst.getOperand(4)); // Rm in processInstruction()
7157 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7158 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7160 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7162 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7164 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7165 TmpInst.addOperand(Inst.getOperand(5)); // CondCode in processInstruction()
7166 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
7167 Inst = TmpInst; in processInstruction()
7178 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7179 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7180 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
7181 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7182 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7184 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7185 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7186 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7187 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7188 Inst = TmpInst; in processInstruction()
7201 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7202 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7203 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7205 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
7206 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7207 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7209 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7210 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7212 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7213 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7214 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7215 Inst = TmpInst; in processInstruction()
7228 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7229 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7230 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7232 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7234 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
7235 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7236 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7238 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7239 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7241 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7243 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7244 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7245 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7246 Inst = TmpInst; in processInstruction()
7259 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7260 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7261 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7263 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7265 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7267 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb in processInstruction()
7268 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7269 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7271 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7272 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7274 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7276 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7278 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7279 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7280 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7281 Inst = TmpInst; in processInstruction()
7292 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7293 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7294 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7295 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7296 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7297 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7298 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7299 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7300 Inst = TmpInst; in processInstruction()
7313 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7314 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7315 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7317 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7318 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7319 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7320 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7322 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7323 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7324 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7325 Inst = TmpInst; in processInstruction()
7338 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7339 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7340 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7342 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7344 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7345 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7346 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7347 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7349 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7351 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7352 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7353 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7354 Inst = TmpInst; in processInstruction()
7367 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7368 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7369 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7371 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7373 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7375 TmpInst.addOperand(Inst.getOperand(2)); // Rn in processInstruction()
7376 TmpInst.addOperand(Inst.getOperand(3)); // alignment in processInstruction()
7377 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) in processInstruction()
7378 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7380 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7382 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7384 TmpInst.addOperand(Inst.getOperand(1)); // lane in processInstruction()
7385 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7386 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7387 Inst = TmpInst; in processInstruction()
7400 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7401 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7402 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7404 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7406 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7407 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7408 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7409 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7410 Inst = TmpInst; in processInstruction()
7422 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7423 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7424 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7426 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7428 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7429 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7430 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7432 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7433 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7434 Inst = TmpInst; in processInstruction()
7446 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7447 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7448 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7450 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7452 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7453 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7454 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7455 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
7456 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7457 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7458 Inst = TmpInst; in processInstruction()
7471 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7472 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7473 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7475 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7477 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7478 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7479 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7480 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7481 Inst = TmpInst; in processInstruction()
7493 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7494 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7495 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7497 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7499 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7500 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7501 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7503 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7504 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7505 Inst = TmpInst; in processInstruction()
7517 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7518 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7519 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7521 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7523 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7524 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7525 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7526 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
7527 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7528 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7529 Inst = TmpInst; in processInstruction()
7542 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7543 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7544 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7546 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7548 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7550 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7551 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7552 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7553 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7554 Inst = TmpInst; in processInstruction()
7566 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7567 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7568 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7570 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7572 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7574 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7575 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7576 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7578 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7579 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7580 Inst = TmpInst; in processInstruction()
7592 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7593 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7594 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7596 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7598 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7600 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7601 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7602 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7603 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
7604 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7605 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7606 Inst = TmpInst; in processInstruction()
7619 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7620 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7621 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7623 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7625 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7627 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7628 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7629 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7630 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7631 Inst = TmpInst; in processInstruction()
7643 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7644 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7645 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7647 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7649 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7651 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7652 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7653 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7655 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7656 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7657 Inst = TmpInst; in processInstruction()
7669 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7670 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7671 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7673 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7675 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7677 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7678 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7679 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7680 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
7681 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7682 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7683 Inst = TmpInst; in processInstruction()
7696 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7697 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7698 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7699 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7700 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7702 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7704 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7705 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7706 Inst = TmpInst; in processInstruction()
7718 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7719 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7720 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7721 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7723 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7724 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7726 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7728 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7729 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7730 Inst = TmpInst; in processInstruction()
7742 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7743 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7744 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7745 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7746 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
7747 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7748 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7750 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7752 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7753 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7754 Inst = TmpInst; in processInstruction()
7767 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7768 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7769 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7770 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7771 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7773 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7775 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7777 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7778 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7779 Inst = TmpInst; in processInstruction()
7791 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7792 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7793 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7794 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7796 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7797 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7799 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7801 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7803 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7804 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7805 Inst = TmpInst; in processInstruction()
7817 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
7818 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7819 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn in processInstruction()
7820 TmpInst.addOperand(Inst.getOperand(2)); // alignment in processInstruction()
7821 TmpInst.addOperand(Inst.getOperand(3)); // Rm in processInstruction()
7822 TmpInst.addOperand(Inst.getOperand(0)); // Vd in processInstruction()
7823 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7825 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7827 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + in processInstruction()
7829 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7830 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7831 Inst = TmpInst; in processInstruction()
7839 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
7840 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && in processInstruction()
7841 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
7845 switch (Inst.getOpcode()) { in processInstruction()
7854 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
7855 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7856 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
7857 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
7858 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
7859 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7860 Inst = TmpInst; in processInstruction()
7873 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
7874 isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
7875 isARMLowRegister(Inst.getOperand(2).getReg()) && in processInstruction()
7876 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && in processInstruction()
7877 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) in processInstruction()
7881 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { in processInstruction()
7889 TmpInst.addOperand(Inst.getOperand(0)); // Rd in processInstruction()
7892 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
7893 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7894 TmpInst.addOperand(Inst.getOperand(2)); // Rm in processInstruction()
7895 TmpInst.addOperand(Inst.getOperand(4)); // CondCode in processInstruction()
7896 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
7899 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
7900 Inst = TmpInst; in processInstruction()
7909 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
7910 isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
7911 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) in processInstruction()
7915 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { in processInstruction()
7923 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); in processInstruction()
7926 TmpInst.addOperand(Inst.getOperand(0)); // Rd in processInstruction()
7929 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
7930 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7933 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7934 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7937 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
7938 Inst = TmpInst; in processInstruction()
7947 switch(Inst.getOpcode()) { in processInstruction()
7957 TmpInst.addOperand(Inst.getOperand(0)); // Rd in processInstruction()
7958 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7959 TmpInst.addOperand(Inst.getOperand(2)); // Rm in processInstruction()
7961 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7962 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7963 TmpInst.addOperand(Inst.getOperand(5)); // cc_out in processInstruction()
7964 Inst = TmpInst; in processInstruction()
7972 switch(Inst.getOpcode()) { in processInstruction()
7980 unsigned Amt = Inst.getOperand(2).getImm(); in processInstruction()
7988 TmpInst.addOperand(Inst.getOperand(0)); // Rd in processInstruction()
7989 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
7992 TmpInst.addOperand(Inst.getOperand(3)); // CondCode in processInstruction()
7993 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
7994 TmpInst.addOperand(Inst.getOperand(5)); // cc_out in processInstruction()
7995 Inst = TmpInst; in processInstruction()
8002 TmpInst.addOperand(Inst.getOperand(0)); // Rd in processInstruction()
8003 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
8005 TmpInst.addOperand(Inst.getOperand(2)); // CondCode in processInstruction()
8006 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8007 TmpInst.addOperand(Inst.getOperand(4)); // cc_out in processInstruction()
8008 Inst = TmpInst; in processInstruction()
8014 if (Inst.getNumOperands() != 5) in processInstruction()
8018 TmpInst.addOperand(Inst.getOperand(4)); // Rt in processInstruction()
8019 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb in processInstruction()
8020 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
8022 TmpInst.addOperand(Inst.getOperand(2)); // CondCode in processInstruction()
8023 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8024 Inst = TmpInst; in processInstruction()
8030 if (Inst.getNumOperands() != 5) in processInstruction()
8034 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb in processInstruction()
8035 TmpInst.addOperand(Inst.getOperand(4)); // Rt in processInstruction()
8036 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
8038 TmpInst.addOperand(Inst.getOperand(2)); // CondCode in processInstruction()
8039 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8040 Inst = TmpInst; in processInstruction()
8047 Inst.getNumOperands() == 5) { in processInstruction()
8050 TmpInst.addOperand(Inst.getOperand(4)); // Rt in processInstruction()
8051 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb in processInstruction()
8052 TmpInst.addOperand(Inst.getOperand(1)); // Rn in processInstruction()
8055 TmpInst.addOperand(Inst.getOperand(2)); // CondCode in processInstruction()
8056 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8057 Inst = TmpInst; in processInstruction()
8065 Inst.getNumOperands() == 5) { in processInstruction()
8068 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb in processInstruction()
8069 TmpInst.addOperand(Inst.getOperand(4)); // Rt in processInstruction()
8070 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 in processInstruction()
8072 TmpInst.addOperand(Inst.getOperand(2)); // CondCode in processInstruction()
8073 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8074 Inst = TmpInst; in processInstruction()
8081 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) in processInstruction()
8083 Inst.setOpcode(ARM::t2ADDri); in processInstruction()
8084 Inst.addOperand(MCOperand::createReg(0)); // cc_out in processInstruction()
8090 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) in processInstruction()
8092 Inst.setOpcode(ARM::t2SUBri); in processInstruction()
8093 Inst.addOperand(MCOperand::createReg(0)); // cc_out in processInstruction()
8100 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
8101 Inst.setOpcode(ARM::tADDi3); in processInstruction()
8110 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
8111 Inst.setOpcode(ARM::tSUBi3); in processInstruction()
8121 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || in processInstruction()
8122 !isARMLowRegister(Inst.getOperand(0).getReg()) || in processInstruction()
8123 (unsigned)Inst.getOperand(2).getImm() > 255 || in processInstruction()
8124 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || in processInstruction()
8125 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || in processInstruction()
8130 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? in processInstruction()
8132 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8133 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
8134 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8135 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
8136 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8137 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
8138 Inst = TmpInst; in processInstruction()
8148 auto DestReg = Inst.getOperand(0).getReg(); in processInstruction()
8149 bool Transform = DestReg == Inst.getOperand(1).getReg(); in processInstruction()
8150 if (!Transform && DestReg == Inst.getOperand(2).getReg()) { in processInstruction()
8155 Inst.getOperand(5).getReg() != 0 || in processInstruction()
8161 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8162 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8163 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2)); in processInstruction()
8164 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8165 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
8166 Inst = TmpInst; in processInstruction()
8172 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { in processInstruction()
8173 Inst.setOpcode(ARM::t2ADDrr); in processInstruction()
8174 Inst.addOperand(MCOperand::createReg(0)); // cc_out in processInstruction()
8181 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { in processInstruction()
8182 Inst.setOpcode(ARM::tBcc); in processInstruction()
8188 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ in processInstruction()
8189 Inst.setOpcode(ARM::t2Bcc); in processInstruction()
8195 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { in processInstruction()
8196 Inst.setOpcode(ARM::t2B); in processInstruction()
8202 if (Inst.getOperand(1).getImm() == ARMCC::AL) { in processInstruction()
8203 Inst.setOpcode(ARM::tB); in processInstruction()
8212 unsigned Rn = Inst.getOperand(0).getReg(); in processInstruction()
8217 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || in processInstruction()
8222 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); in processInstruction()
8226 Inst.insert(Inst.begin(), in processInstruction()
8227 MCOperand::createReg(Inst.getOperand(0).getReg())); in processInstruction()
8236 unsigned Rn = Inst.getOperand(0).getReg(); in processInstruction()
8238 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { in processInstruction()
8241 Inst.setOpcode(ARM::t2STMIA_UPD); in processInstruction()
8251 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) in processInstruction()
8254 Inst.setOpcode(ARM::t2LDMIA_UPD); in processInstruction()
8256 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8257 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8262 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) in processInstruction()
8265 Inst.setOpcode(ARM::t2STMDB_UPD); in processInstruction()
8267 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8268 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
8274 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
8275 (unsigned)Inst.getOperand(1).getImm() <= 255 && in processInstruction()
8276 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && in processInstruction()
8277 Inst.getOperand(4).getReg() == ARM::CPSR) || in processInstruction()
8278 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && in processInstruction()
8284 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8285 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
8286 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8287 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
8288 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8289 Inst = TmpInst; in processInstruction()
8297 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
8298 isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
8299 Inst.getOperand(2).getImm() == ARMCC::AL && in processInstruction()
8300 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
8305 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); in processInstruction()
8306 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8307 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8308 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
8309 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8310 Inst = TmpInst; in processInstruction()
8321 if (isARMLowRegister(Inst.getOperand(0).getReg()) && in processInstruction()
8322 isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
8323 Inst.getOperand(2).getImm() == 0 && in processInstruction()
8327 switch (Inst.getOpcode()) { in processInstruction()
8337 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8338 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8339 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8340 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
8341 Inst = TmpInst; in processInstruction()
8347 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); in processInstruction()
8351 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { in processInstruction()
8355 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8356 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8357 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8358 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
8359 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
8360 Inst = TmpInst; in processInstruction()
8372 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); in processInstruction()
8374 switch (Inst.getOpcode()) { in processInstruction()
8385 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && in processInstruction()
8389 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8390 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8391 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
8392 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
8393 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
8394 TmpInst.addOperand(Inst.getOperand(6)); in processInstruction()
8395 Inst = TmpInst; in processInstruction()
8406 MCOperand &MO = Inst.getOperand(1); in processInstruction()
8410 if ((Inst.getOperand(0).getImm() & 1) == 0) { in processInstruction()
8419 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); in processInstruction()
8433 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
8434 isARMLowRegister(Inst.getOperand(2).getReg())) && in processInstruction()
8435 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && in processInstruction()
8436 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || in processInstruction()
8437 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && in processInstruction()
8442 switch (Inst.getOpcode()) { in processInstruction()
8453 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8454 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
8455 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8456 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
8457 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8458 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
8459 Inst = TmpInst; in processInstruction()
8472 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && in processInstruction()
8473 isARMLowRegister(Inst.getOperand(2).getReg())) && in processInstruction()
8474 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || in processInstruction()
8475 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && in processInstruction()
8476 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || in processInstruction()
8477 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && in processInstruction()
8482 switch (Inst.getOpcode()) { in processInstruction()
8491 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8492 TmpInst.addOperand(Inst.getOperand(5)); in processInstruction()
8493 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { in processInstruction()
8494 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8495 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
8497 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
8498 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8500 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8501 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
8502 Inst = TmpInst; in processInstruction()
8511 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { in checkTargetMatchPredicate() argument
8514 unsigned Opc = Inst.getOpcode(); in checkTargetMatchPredicate()
8519 assert(MCID.NumOperands == Inst.getNumOperands() && in checkTargetMatchPredicate()
8528 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) in checkTargetMatchPredicate()
8532 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && in checkTargetMatchPredicate()
8535 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
8542 isARMLowRegister(Inst.getOperand(1).getReg()) && in checkTargetMatchPredicate()
8543 isARMLowRegister(Inst.getOperand(2).getReg())) in checkTargetMatchPredicate()
8547 isARMLowRegister(Inst.getOperand(0).getReg()) && in checkTargetMatchPredicate()
8548 isARMLowRegister(Inst.getOperand(1).getReg())) in checkTargetMatchPredicate()
8555 if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops()) in checkTargetMatchPredicate()
8557 else if (Inst.getOperand(I).getReg() == ARM::PC) in checkTargetMatchPredicate()
8575 MCInst Inst; in MatchAndEmitInstruction() local
8578 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, in MatchAndEmitInstruction()
8584 if (validateInstruction(Inst, Operands)) { in MatchAndEmitInstruction()
8598 while (processInstruction(Inst, Operands, Out)) in MatchAndEmitInstruction()
8603 !isV8EligibleForIT(&Inst)) { in MatchAndEmitInstruction()
8615 if (Inst.getOpcode() == ARM::ITasm) in MatchAndEmitInstruction()
8618 Inst.setLoc(IDLoc); in MatchAndEmitInstruction()
8619 Out.EmitInstruction(Inst, getSTI()); in MatchAndEmitInstruction()