Lines Matching refs:ShiftReg
517 unsigned ShiftReg; member
1730 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
2543 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
2548 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
2838 << " " << RegShiftedReg.ShiftReg << ">"; in print()
3004 int ShiftReg = 0; in tryParseShiftRegister() local
3009 ShiftReg = SrcReg; in tryParseShiftRegister()
3044 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
3045 if (ShiftReg == -1) { in tryParseShiftRegister()
3056 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
3058 ShiftReg, Imm, in tryParseShiftRegister()