Lines Matching refs:Vd
1239 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1243 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1244 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1249 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1252 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1263 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1267 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1268 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
1274 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1277 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
5057 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); in DecodeVCVTD() local
5058 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); in DecodeVCVTD()
5101 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeVCVTD()
5116 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); in DecodeVCVTQ() local
5117 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); in DecodeVCVTQ()
5160 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeVCVTQ()