114                                   unsigned DestReg, unsigned SrcReg,  in copyPhysReg()  argument
117   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
118     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);  in copyPhysReg()
120   AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)  in copyPhysReg()
167                      unsigned DestReg, int FI,  in loadRegFromStackSlot()  argument
181     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)  in loadRegFromStackSlot()
191     MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);  in loadRegFromStackSlot()
194     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
195     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
199     if (TargetRegisterInfo::isPhysicalRegister(DestReg))  in loadRegFromStackSlot()
200       MIB.addReg(DestReg, RegState::ImplicitDefine);  in loadRegFromStackSlot()
204   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);  in loadRegFromStackSlot()
218                                unsigned DestReg, unsigned BaseReg, int NumBytes,  in emitT2RegPlusImmediate()  argument
221   if (NumBytes == 0 && DestReg != BaseReg) {  in emitT2RegPlusImmediate()
222     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)  in emitT2RegPlusImmediate()
233   if (DestReg != ARM::SP && DestReg != BaseReg &&  in emitT2RegPlusImmediate()
239       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)  in emitT2RegPlusImmediate()
245       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)  in emitT2RegPlusImmediate()
246         .addReg(DestReg)  in emitT2RegPlusImmediate()
254         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)  in emitT2RegPlusImmediate()
256           .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
265         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)  in emitT2RegPlusImmediate()
267           .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
278     if (DestReg == ARM::SP && BaseReg != ARM::SP) {  in emitT2RegPlusImmediate()
280       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)  in emitT2RegPlusImmediate()
289       if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {  in emitT2RegPlusImmediate()
292         AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
311       assert(DestReg != ARM::SP && BaseReg != ARM::SP);  in emitT2RegPlusImmediate()
331       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
337     BaseReg = DestReg;  in emitT2RegPlusImmediate()