Lines Matching refs:PredR
165 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
169 MachineBasicBlock::iterator Where, unsigned PredR, bool Cond);
170 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
775 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred() argument
788 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(MI))) in getReachingDefForPred()
798 if (RR.Reg == PredR) { in getReachingDefForPred()
887 MachineBasicBlock::iterator Where, unsigned PredR, bool Cond) { in predicateAt() argument
915 MB.addReg(PredR); in predicateAt()
941 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange() argument
950 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(MI))) in renameInRange()
986 unsigned PredR = MP.getReg(); in predicate() local
987 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); in predicate()
1004 if (!I->modifiesRegister(PredR, 0)) in predicate()
1017 if (PredValid && HII->isPredicated(MI) && MI->readsRegister(PredR)) in predicate()
1073 predicateAt(RD, DefI, PastDefIt, PredR, Cond); in predicate()
1075 predicateAt(RD, DefI, TfrIt, PredR, Cond); in predicate()
1080 renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt); in predicate()