Lines Matching refs:RegVT

1068       EVT RegVT = VA.getLocVT();  in LowerFormalArguments()  local
1069 if (RegVT == MVT::i8 || RegVT == MVT::i16 || in LowerFormalArguments()
1070 RegVT == MVT::i32 || RegVT == MVT::f32) { in LowerFormalArguments()
1074 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1075 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) { in LowerFormalArguments()
1079 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1082 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || in LowerFormalArguments()
1083 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { in LowerFormalArguments()
1087 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1089 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || in LowerFormalArguments()
1090 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { in LowerFormalArguments()
1094 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1097 } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || in LowerFormalArguments()
1098 RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) { in LowerFormalArguments()
1102 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1104 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || in LowerFormalArguments()
1105 RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { in LowerFormalArguments()
1109 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
1110 } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) { in LowerFormalArguments()
1115 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()