Lines Matching refs:IntRegs
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
70 (ins IntRegs:$src1, ImmOp:$src2),
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
98 (MI IntRegs:$src1, ImmPred:$src2)>;
121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
229 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
230 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
257 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
289 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
290 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
300 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
301 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
320 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
321 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
351 : ALU32_ri <(outs IntRegs:$Rd),
352 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
377 : ALU32_ri <(outs IntRegs:$Rd),
378 (ins IntRegs:$Rs, immOp:$s16),
429 : ALU32_ri <(outs IntRegs:$Rd),
430 (ins IntRegs:$Rs, s10Ext:$s10),
432 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> {
455 def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
477 def: Pat<(sub s32ImmPred:$s10, IntRegs:$Rs),
478 (A2_subri imm:$s10, IntRegs:$Rs)>;
481 def: Pat<(not (i32 IntRegs:$src1)),
482 (A2_subri -1, IntRegs:$src1)>;
486 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
507 : ALU32Inst<(outs IntRegs:$dst),
508 (ins PredRegs:$src1, IntRegs:$src2),
530 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
595 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
624 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
625 [(set (i32 IntRegs:$Rd), s32ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
669 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
686 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
690 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
702 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
705 [(set (i32 IntRegs:$Rd),
734 ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
755 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
809 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
1013 (outs PredRegs:$Pd), (ins IntRegs:$Rs, s8Ext:$s8),
1016 (outs PredRegs:$Pd), (ins IntRegs:$Rs, u8Ext:$s8),
1041 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1124 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1140 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1182 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1188 (Inst IntRegs:$src1, IntRegs:$src2)>;
1194 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1390 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1500 : JRInst<(outs), (ins IntRegs:$dst),
1512 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1550 dag InputDag = (ins IntRegs:$Rs)>
1572 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1573 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1606 def: Pat<(brind (i32 IntRegs:$dst)),
1607 (J2_jumpr IntRegs:$dst)>;
1621 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1654 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1710 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1711 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1715 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1716 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1720 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1726 def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>;
1727 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
1739 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1772 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1773 (VT (MI IntRegs:$Rs, imm:$Off))>;
1774 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1800 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1801 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1812 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1813 (ins IntRegs:$src1, ImmOp:$offset),
1846 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1847 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1904 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1905 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1910 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1911 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1916 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1925 def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
1926 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
1938 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2),
1939 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1974 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1975 (ins IntRegs:$src1, ModRegs:$src2),
1995 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
1996 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
1997 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
1998 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
1999 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
2001 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
2011 (ins IntRegs:$addr, s11_2Ext:$off),
2028 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
2029 (ins IntRegs:$Rz, ModRegs:$Mu),
2050 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
2051 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
2055 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
2056 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
2057 def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>;
2058 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
2062 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
2075 : LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_),
2076 (ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu),
2105 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
2106 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
2134 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
2135 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
2140 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
2141 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2142 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
2143 def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>;
2148 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2168 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
2169 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4Imm:$src4),
2173 def L2_loadrb_pci_pseudo : T_load_pci_pseudo <"memb", IntRegs>;
2174 def L2_loadrub_pci_pseudo : T_load_pci_pseudo <"memub", IntRegs>;
2175 def L2_loadrh_pci_pseudo : T_load_pci_pseudo <"memh", IntRegs>;
2176 def L2_loadruh_pci_pseudo : T_load_pci_pseudo <"memuh", IntRegs>;
2177 def L2_loadri_pci_pseudo : T_load_pci_pseudo <"memw", IntRegs>;
2193 (ins IntRegs:$src),
2205 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
2212 : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt),
2228 def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>;
2240 <(outs RC:$dst, IntRegs:$_dst_),
2241 (ins IntRegs:$Rz, ModRegs:$Mu),
2263 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
2264 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
2265 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
2266 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
2267 def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
2268 def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
2269 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2288 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
2289 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2293 def L2_loadrb_pbr_pseudo : T_load_pbr_pseudo <"memb", IntRegs>;
2294 def L2_loadrub_pbr_pseudo : T_load_pbr_pseudo <"memub", IntRegs>;
2295 def L2_loadrh_pbr_pseudo : T_load_pbr_pseudo <"memh", IntRegs>;
2296 def L2_loadruh_pbr_pseudo : T_load_pbr_pseudo <"memuh", IntRegs>;
2297 def L2_loadri_pbr_pseudo : T_load_pbr_pseudo <"memw", IntRegs>;
2331 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2417 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2509 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2643 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2674 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2678 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2718 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2737 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32ImmPred:$u8))]>;
2740 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2745 def M2_mpyui : MInst<(outs IntRegs:$dst),
2746 (ins IntRegs:$src1, IntRegs:$src2),
2756 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2758 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2765 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2786 : MInst < (outs IntRegs:$dst),
2787 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2809 [(set (i32 IntRegs:$dst),
2810 (add (mul IntRegs:$src2, u32ImmPred:$src3),
2811 IntRegs:$src1))]>, ImmRegRel;
2814 [(set (i32 IntRegs:$dst),
2815 (add (mul IntRegs:$src2, IntRegs:$src3),
2816 IntRegs:$src1))]>, ImmRegRel;
2822 [(set (i32 IntRegs:$dst),
2823 (add (add (i32 IntRegs:$src2), s32ImmPred:$src3),
2824 (i32 IntRegs:$src1)))]>, ImmRegRel;
2827 [(set (i32 IntRegs:$dst),
2828 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2829 (i32 IntRegs:$src1)))]>, ImmRegRel;
2847 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2848 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2851 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2852 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3041 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
3104 (ins IntRegs:$Rs, IntRegs:$Rt),
3132 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
3205 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
3206 (i64 (anyext (i32 IntRegs:$src2))))),
3207 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
3209 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
3210 (i64 (sext (i32 IntRegs:$src2))))),
3211 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
3221 (mul (i64 (sext (i32 IntRegs:$src2))),
3222 (i64 (sext (i32 IntRegs:$src3)))))),
3223 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3226 (mul (i64 (sext (i32 IntRegs:$src2))),
3227 (i64 (sext (i32 IntRegs:$src3)))))),
3228 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3231 (mul (i64 (anyext (i32 IntRegs:$src2))),
3232 (i64 (anyext (i32 IntRegs:$src3)))))),
3233 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3236 (mul (i64 (zext (i32 IntRegs:$src2))),
3237 (i64 (zext (i32 IntRegs:$src3)))))),
3238 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3241 (mul (i64 (anyext (i32 IntRegs:$src2))),
3242 (i64 (anyext (i32 IntRegs:$src3)))))),
3243 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3246 (mul (i64 (zext (i32 IntRegs:$src2))),
3247 (i64 (zext (i32 IntRegs:$src3)))))),
3248 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3286 : STInst <(outs IntRegs:$_dst_),
3287 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
3322 : STInst <(outs IntRegs:$_dst_),
3323 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
3377 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
3380 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
3383 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
3389 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
3406 : STInst <(outs IntRegs:$_dst_),
3407 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
3428 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
3429 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
3430 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
3432 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
3438 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
3474 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
3534 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
3537 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
3540 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
3547 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
3567 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3568 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
3570 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3571 (MI IntRegs:$Rs, 0, Value:$Rt)>;
3586 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3587 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
3590 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3591 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
3652 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
3675 : STInst <(outs IntRegs:$_dst_),
3676 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3703 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3705 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3707 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3709 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3717 : NVInst < (outs IntRegs:$_dst_),
3718 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3756 : STInstPI<(outs IntRegs:$_dst_),
3757 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3, s4Imm:$src4),
3761 def S2_storerb_pci_pseudo : T_store_pci_pseudo <"memb", IntRegs>;
3762 def S2_storerh_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
3763 def S2_storerf_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
3764 def S2_storeri_pci_pseudo : T_store_pci_pseudo <"memw", IntRegs>;
3773 : STInst <(outs IntRegs:$_dst_),
3774 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3796 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3797 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3798 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3800 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3809 : NVInst <(outs IntRegs:$_dst_),
3810 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3842 <(outs IntRegs:$_dst_),
3843 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3865 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3868 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3871 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3875 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3884 : NVInst <(outs IntRegs:$_dst_),
3885 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3921 : STInstPI<(outs IntRegs:$_dst_),
3922 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3),
3926 def S2_storerb_pbr_pseudo : T_store_pbr_pseudo <"memb", IntRegs>;
3927 def S2_storerh_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
3928 def S2_storeri_pbr_pseudo : T_store_pbr_pseudo <"memw", IntRegs>;
3929 def S2_storerf_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
3959 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3963 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3967 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
4036 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
4037 (i32 (sub 0, (i32 IntRegs:$src))),
4038 (i32 IntRegs:$src))),
4039 (A2_abs IntRegs:$src)>;
4042 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
4043 (i32 IntRegs:$src)),
4044 (sra (i32 IntRegs:$src), (i32 31)))),
4045 (A2_abs IntRegs:$src)>;
4071 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
4075 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
4080 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
4085 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
4107 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
4112 def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src),
4118 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
4185 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
4189 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
4227 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
4243 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
4263 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
4264 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4265 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4266 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4267 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4268 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4269 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
4270 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4271 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4272 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4273 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4274 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
4280 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
4297 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4315 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
4316 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4317 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
4318 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4319 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
4320 (S2_tstbit_i IntRegs:$Rs, 0)>;
4327 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
4344 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4364 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
4365 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
4366 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
4367 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
4371 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
4372 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
4389 def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add (i32 IntRegs:$b), 3))),
4391 (i32 (zextloadi8 (add (i32 IntRegs:$b), 2)))),
4393 (shl (i32 (zextloadi8 (add (i32 IntRegs:$b), 1))), (i32 8))),
4394 (zextloadi8 (i32 IntRegs:$b))),
4395 (A2_swiz (L2_loadri_io IntRegs:$b, 0))>;
4407 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
4421 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
4440 def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32ImmPred:$Off))),
4441 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
4442 def: Pat<(i1 (load (i32 IntRegs:$Rs))),
4443 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
4491 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
4492 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
4494 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
4495 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
4558 def TFR_FI : ALU32_ri<(outs IntRegs:$Rd),
4559 (ins IntRegs:$fi, s32Imm:$off), "">;
4560 def TFR_FIA : ALU32_ri<(outs IntRegs:$Rd),
4561 (ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">;
4591 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
4663 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
4690 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2),
4733 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
4735 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
4736 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
4755 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
4757 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
4758 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
4762 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
4783 : ALU32_ri<(outs IntRegs:$dst),
4806 def LO_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4811 def HI_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4817 def HI_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4823 def LO_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4829 def HI_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4835 def LO_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4843 def CONST32 : CONSTLDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4845 [(set (i32 IntRegs:$dst),
4849 def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
4851 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4919 def: Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4920 (TCRETURNr IntRegs:$dst)>;
4923 def: Pat<(and (i32 IntRegs:$src1), 65535),
4924 (A2_zxth IntRegs:$src1)>;
4927 def: Pat<(and (i32 IntRegs:$src1), 255),
4928 (A2_zxtb IntRegs:$src1)>;
4943 (i32 IntRegs:$src3)),
4944 (C2_muxir PredRegs:$src1, IntRegs:$src3, s32ImmPred:$src2)>;
4948 def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32ImmPred:$src3),
4949 (C2_muxri PredRegs:$src1, s32ImmPred:$src3, IntRegs:$src2)>;
4969 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4971 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4974 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4976 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4985 def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset),
4986 (J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ImmPred:$src2)),
5014 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
5015 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
5018 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5019 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
5029 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
5030 (C2_not (C2_cmpeqi IntRegs:$src1, s32ImmPred:$src2))>;
5043 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5044 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
5048 def: Pat<(i1 (setge (i32 IntRegs:$src1), s32ImmPred:$src2)),
5049 (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
5060 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
5061 (C2_not (C2_cmpgti IntRegs:$src1,
5065 def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)),
5066 (C2_cmpeq IntRegs:$src1, IntRegs:$src1)>;
5069 def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32ImmPred:$src2)),
5070 (C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32ImmPred:$src2))>;
5073 def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32ImmPred:$src2)),
5074 (C2_cmpgtui IntRegs:$src1, u32ImmPred:$src2)>;
5136 def ALLOCA: ALU32Inst<(outs IntRegs:$Rd),
5137 (ins IntRegs:$Rs, u32Imm:$A), "",
5138 [(set (i32 IntRegs:$Rd),
5139 (HexagonALLOCA (i32 IntRegs:$Rs), (i32 imm:$A)))]>;
5142 def ALIGNA : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>;
5147 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
5149 [(set (i32 IntRegs:$dst),
5150 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
5153 def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
5154 (i32 IntRegs:$src1)>;
5176 : SInst_acc<(outs IntRegs:$Rx),
5177 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
5179 [(set (i32 IntRegs:$Rx),
5180 (OpNode2 (i32 IntRegs:$src1),
5181 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
5206 : SInst_acc<(outs IntRegs:$Rx),
5207 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
5209 [(set (i32 IntRegs:$Rx),
5210 (OpNode2 (i32 IntRegs:$src1),
5211 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
5264 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
5268 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
5421 (ins RC:$src1, IntRegs:$src2),
5430 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
5440 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
5441 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
5442 (i32 IntRegs:$src2)))]>;
5446 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5452 (i32 IntRegs:$src2)))]>;
5485 : SInst < (outs IntRegs:$Rd),
5486 (ins DoubleRegs:$Rss, IntRegs:$Rt),
5550 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5588 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5589 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5632 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5690 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5713 def: Pat<(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5714 (M2_mpysin IntRegs:$src1, u8ImmPred:$src2)>;
5722 : SInst <(outs IntRegs:$Rx),
5723 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5753 : SInst <(outs IntRegs:$Rx),
5754 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, u5Imm:$u5),