Lines Matching refs:Rd
121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
122 "$Rd = "#mnemonic#"($Rs, $Rt)",
130 bits<5> Rd;
138 let Inst{4-0} = Rd;
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
146 "$Rd = "#mnemonic#"($Rs, $Rt)",
157 bits<5> Rd;
168 let Inst{4-0} = Rd;
174 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
185 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
239 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in {
300 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
302 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
303 bits<5> Rd;
317 let Inst{4-0} = Rd;
351 : ALU32_ri <(outs IntRegs:$Rd),
353 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
354 ") $Rd = ")#"add($Rs, #$s8)"> {
355 bits<5> Rd;
369 let Inst{4-0} = Rd;
377 : ALU32_ri <(outs IntRegs:$Rd),
379 "$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> {
380 bits<5> Rd;
389 let Inst{4-0} = Rd;
423 // Rd=and(Rs,#s10)
424 // Rd=or(Rs,#s10)
429 : ALU32_ri <(outs IntRegs:$Rd),
431 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
432 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> {
433 bits<5> Rd;
445 let Inst{4-0} = Rd;
455 def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
456 "$Rd = sub(#$s10, $Rs)", []>, ImmRegRel {
457 bits<5> Rd;
467 let Inst{4-0} = Rd;
480 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
504 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
595 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
596 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
601 bits<5> Rd;
612 let Inst{4-0} = Rd;
624 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
625 [(set (i32 IntRegs:$Rd), s32ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
627 bits<5> Rd;
633 let Inst{4-0} = Rd;
669 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
670 bits<5> Rd;
682 let Inst{4-0} = Rd;
687 "$Rd = mux($Pu, #$s8, $Rs)">;
691 "$Rd = mux($Pu, $Rs, #$s8)">;
702 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
704 "$Rd = mux($Pu, #$s8, #$S8)" ,
705 [(set (i32 IntRegs:$Rd),
707 bits<5> Rd;
719 let Inst{4-0} = Rd;
723 def MUX64_rr : ALU64_rr<(outs DoubleRegs:$Rd),
734 ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
735 "$Rd = "#mnemonic#"($Rs)", [] > {
736 bits<5> Rd;
744 let Inst{4-0} = Rd;
755 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
757 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
758 bits<5> Rd;
769 let Inst{4-0} = Rd;
802 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
809 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
810 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
811 bits<5> Rd;
818 let Inst{4-0} = Rd;
824 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
1033 // Rd=add(Rt.L,Rs.[HL])[:sat]
1034 // Rd=sub(Rt.L,Rs.[HL])[:sat]
1035 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
1036 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
1041 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1042 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
1047 bits<5> Rd;
1057 let Inst{4-0} = Rd;
1062 //Rd=sub(Rt.L,Rs.[LH])
1066 //Rd=add(Rt.L,Rs.[LH])
1071 //Rd=sub(Rt.L,Rs.[LH]):sat
1075 //Rd=add(Rt.L,Rs.[LH]):sat
1080 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
1086 //Rd=add(Rt.[LH],Rs.[LH]):<<16
1093 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
1099 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
1124 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1126 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1127 bits<5> Rd;
1135 let Inst{4-0} = Rd;
1140 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1141 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
1143 bits<5> Rd;
1152 let Inst{4-0} = Rd;
1241 def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd),
1243 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1246 bits<5> Rd;
1256 let Inst{4-0} = Rd;
1262 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1263 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1270 bits<5> Rd;
1278 let Inst{4-0} = Rd;
1390 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1391 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1392 bits<5> Rd;
1401 let Inst{4-0} = Rd;
1405 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1406 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1407 bits<5> Rd;
1413 let Inst{4-0} = Rd;
1922 // Rd=memb[u]h(Rx++#s4:1)
2325 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2331 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2332 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2338 bits<5> Rd;
2350 let Inst{4-0} = Rd;
2355 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2365 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2375 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
2385 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2386 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2718 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2719 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
2721 bits<5> Rd;
2730 let Inst{4-0} = Rd;
2737 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32ImmPred:$u8))]>;
2740 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2749 // Rd=mpyi(Rs,#m9)
2751 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
4170 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
4172 bits<5> Rd;
4180 let Inst{4-0} = Rd;
4185 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
4189 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
4227 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
4228 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
4229 bits<5> Rd;
4238 let Inst{4-0} = Rd;
4243 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
4244 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
4245 bits<5> Rd;
4253 let Inst{4-0} = Rd;
4407 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
4408 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
4409 bits<5> Rd;
4416 let Inst{4-0} = Rd;
4491 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
4493 "$Rd = addasl($Rt, $Rs, #$u3)" ,
4494 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
4497 bits<5> Rd;
4509 let Inst{4-0} = Rd;
4558 def TFR_FI : ALU32_ri<(outs IntRegs:$Rd),
4560 def TFR_FIA : ALU32_ri<(outs IntRegs:$Rd),
4757 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
4758 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
5136 def ALLOCA: ALU32Inst<(outs IntRegs:$Rd),
5138 [(set (i32 IntRegs:$Rd),
5142 def ALIGNA : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>;
5467 // Rd=[asr|lsr|asl|lsl](Rs,Rt)
5475 // Rd=asr(Rs,Rt):sat
5476 // Rd=asl(Rs,Rt):sat
5485 : SInst < (outs IntRegs:$Rd),
5487 "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")"
5492 bits<5> Rd;
5502 let Inst{4-0} = Rd;
5632 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5633 "$Rd = "#mnemonic#"($Rs, $Rtt)",
5635 bits<5> Rd;
5645 let Inst{4-0} = Rd;
5686 // Rd=extractu(Rs,Rtt)
5687 // Rd=extractu(Rs,#u5,#U5)
5712 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)