Lines Matching refs:IntRegs
45 : V6_LDInst <(outs VectorRegs:$dst), (ins IntRegs:$src1, s4_6Imm:$src2),
50 : V6_LDInst <(outs VectorRegs128B:$dst), (ins IntRegs:$src1, s4_7Imm:$src2),
108 : V6_STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
147 : V6_STInst <(outs ), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
178 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
240 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
279 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
324 : V6_LDInst <(outs RC:$dst, IntRegs:$_dst_),
325 (ins IntRegs:$src1, ImmOp:$src2), asmStr, [],
390 : V6_STInst <(outs IntRegs:$_dst_),
391 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
431 : V6_STInst <(outs IntRegs:$_dst_),
432 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
465 : V6_STInst<(outs IntRegs:$_dst_),
466 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
528 : V6_STInst <(outs IntRegs:$_dst_),
529 (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
569 : V6_STInst <(outs IntRegs:$_dst_),
570 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
615 : V6_LDInst <(outs VectorRegs:$dst, IntRegs:$_dst_),
616 (ins IntRegs:$src1, ModRegs:$src2), asmStr, [],
648 : V6_STInst <(outs IntRegs:$_dst_),
649 (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3),
670 : V6_STInst <(outs IntRegs:$_dst_),
671 (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3),
686 : V6_STInst<(outs IntRegs:$_dst_),
687 (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
718 : V6_STInst <(outs IntRegs:$_dst_),
719 (ins VecPredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
737 : V6_STInst <(outs IntRegs:$_dst_),
738 (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
761 VSTInst<(outs), (ins IntRegs:$addr, ImmOp:$off, RC:$src),
770 def : Pat<(store (VTSgl VecDblRegs:$src1), IntRegs:$addr),
771 (STrivv_indexed IntRegs:$addr, #0, (VTSgl VecDblRegs:$src1))>,
774 def : Pat<(store (VTDbl VecDblRegs128B:$src1), IntRegs:$addr),
775 (STrivv_indexed_128B IntRegs:$addr, #0,
788 def : Pat<(store (VTSgl VectorRegs:$src1), IntRegs:$addr),
789 (V6_vS32b_ai IntRegs:$addr, #0, (VTSgl VectorRegs:$src1))>,
793 def : Pat<(store (VTDbl VectorRegs128B:$src1), IntRegs:$addr),
794 (V6_vS32b_ai_128B IntRegs:$addr, #0, (VTDbl VectorRegs128B:$src1))>,
800 (add IntRegs:$src2, s4_6ImmPred:$offset)),
801 (V6_vS32b_ai IntRegs:$src2, s4_6ImmPred:$offset,
808 (add IntRegs:$src2, s4_7ImmPred:$offset)),
809 (V6_vS32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset,
821 : V6_LDInst <(outs RC:$dst), (ins IntRegs:$addr, ImmOp:$off),
830 def : Pat < (VTSgl (load IntRegs:$addr)),
831 (LDrivv_indexed IntRegs:$addr, #0) >,
834 def : Pat < (VTDbl (load IntRegs:$addr)),
835 (LDrivv_indexed_128B IntRegs:$addr, #0) >,
846 def : Pat < (VTSgl (load IntRegs:$addr)),
847 (V6_vL32b_ai IntRegs:$addr, #0) >,
851 def : Pat < (VTDbl (load IntRegs:$addr)),
852 (V6_vL32b_ai_128B IntRegs:$addr, #0) >,
857 def : Pat<(VTDbl (load (add IntRegs:$src2, s4_7ImmPred:$offset))),
858 (V6_vL32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>,
862 def : Pat<(VTSgl (load (add IntRegs:$src2, s4_6ImmPred:$offset))),
863 (V6_vL32b_ai IntRegs:$src2, s4_6ImmPred:$offset)>,
876 (ins IntRegs:$base, s32Imm:$offset, VecPredRegs:$src1),
882 (ins IntRegs:$base, s32Imm:$offset, VectorRegs:$src1),
888 (ins IntRegs:$base, s32Imm:$offset, VecPredRegs128B:$src1),
894 (ins IntRegs:$base, s32Imm:$offset, VectorRegs128B:$src1),
904 (ins IntRegs:$base, s32Imm:$offset),
909 (ins IntRegs:$base, s32Imm:$offset),
914 (ins IntRegs:$base, s32Imm:$offset),
919 (ins IntRegs:$base, s32Imm:$offset),
929 (ins IntRegs:$base, s32Imm:$offset, VectorRegs:$src1),
934 (ins IntRegs:$base, s32Imm:$offset, VectorRegs128B:$src1),
943 (ins IntRegs:$base, s32Imm:$offset, VecDblRegs:$src1),
948 (ins IntRegs:$base, s32Imm:$offset, VecDblRegs128B:$src1),
958 (ins IntRegs:$base, s32Imm:$offset),
963 (ins IntRegs:$base, s32Imm:$offset),
972 (ins IntRegs:$base, s32Imm:$offset),
977 (ins IntRegs:$base, s32Imm:$offset),
1001 def : Pat <(v16i32 (selectcc (i32 IntRegs:$lhs), (i32 IntRegs:$rhs),
1004 (v16i32 (VSelectPseudo_V6 (i32 (C2_cmpeq (i32 IntRegs:$lhs),
1005 (i32 IntRegs:$rhs))),
1012 : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2),
1273 !if(!eq (!cast<string>(RCin2), "IntRegs"), "", "128B"))>;
1277 T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, IntRegs, CVI_VX>;
1280 T_HVX_vmpyacc_both <asmString, VectorRegs, VecDblRegs, IntRegs, CVI_VX_DV>;
1283 T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, IntRegs, CVI_VX_DV>;
1286 T_HVX_vmpyacc_both <asmString, VecDblRegs, VecDblRegs, IntRegs, CVI_VX_DV>;
1739 (ins RC:$_src_, RC:$src1, IntRegs:$src2, u1Imm:$src3),
1763 : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, IntRegs:$src2, u1Imm:$src3),
1786 (ins RC:$src1, RC:$src2, IntRegs:$src3),
1982 (ins RCout:$_src_, RCin:$src1, IntRegs:$src2),
1992 (ins RCout:$_src_, RCin:$src1, IntRegs:$src2),
2002 (ins RCin:$src1, IntRegs:$src2),
2011 : CVI_VX_Resource_late<(outs RC:$dst), (ins IntRegs:$src1),
2021 : CVI_VX_Resource_late<(outs RC:$dst), (ins RC:$_src_, IntRegs:$src1),
2032 : CVI_VA_Resource1<(outs RC:$dst), (ins IntRegs:$src1),
2040 : CVI_VX_Resource_late<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2),
2052 : T_HVX_rol <asmString, IntRegs, u5Imm>;
2069 : T_HVX_rol_acc <asmString, IntRegs, u5Imm>;
2097 : LD1Inst <(outs IntRegs:$dst), (ins RC:$src1, IntRegs:$src2),
2117 class T_sys1op_R <string asmString> : T_sys1op <asmString, IntRegs>;
2130 def Y5_l2locka : ST1Inst <(outs PredRegs:$dst), (ins IntRegs:$src1),