Lines Matching refs:Pat
25 def : Pat <(b (bitconvert (a IntRegs:$src))),
27 def : Pat <(a (bitconvert (b IntRegs:$src))),
32 def : Pat <(b (bitconvert (a DoubleRegs:$src))),
34 def : Pat <(a (bitconvert (b DoubleRegs:$src))),
39 def : Pat <(b (bitconvert (a VectorRegs:$src))),
41 def : Pat <(a (bitconvert (b VectorRegs:$src))),
46 def : Pat <(b (bitconvert (a VecDblRegs:$src))),
48 def : Pat <(a (bitconvert (b VecDblRegs:$src))),
53 def : Pat <(b (bitconvert (a VecPredRegs:$src))),
55 def : Pat <(a (bitconvert (b VectorRegs:$src))),
60 def : Pat <(b (bitconvert (a VecDblRegs128B:$src))),
62 def : Pat <(a (bitconvert (b VecDblRegs128B:$src))),
118 def : Pat<(v2i16 (add (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
121 def : Pat<(v2i16 (sub (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
138 def: Pat<(v4i8 (HexagonVSPLATB I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
142 def: Pat<(v4i16 (HexagonVSPLATH I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
146 : Pat <(Op Type:$Rss, Type:$Rtt),
170 def: Pat<(v2i32 (sra V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
173 def: Pat<(v2i32 (srl V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
176 def: Pat<(v2i32 (shl V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
180 def: Pat<(v4i16 (sra V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4ImmPred:$c)))))),
182 def: Pat<(v4i16 (srl V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4ImmPred:$c)))))),
184 def: Pat<(v4i16 (shl V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4ImmPred:$c)))))),
200 def: Pat<(v2i32 (HexagonVSRAW V2I32:$Rs, u5ImmPred:$u5)),
202 def: Pat<(v4i16 (HexagonVSRAH V4I16:$Rs, u4ImmPred:$u4)),
204 def: Pat<(v2i32 (HexagonVSRLW V2I32:$Rs, u5ImmPred:$u5)),
206 def: Pat<(v4i16 (HexagonVSRLH V4I16:$Rs, u4ImmPred:$u4)),
208 def: Pat<(v2i32 (HexagonVSHLW V2I32:$Rs, u5ImmPred:$u5)),
210 def: Pat<(v4i16 (HexagonVSHLH V4I16:$Rs, u4ImmPred:$u4)),
226 : Pat <(Op Value:$Rs, I32:$Rt),
256 : Pat <(i1 (Op Value:$Rs, Value:$Rt)),
273 : Pat <(OutTy (Op InVal:$Rs, InVal:$Rt)),
304 def: Pat<(v4i8 (add (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
309 def: Pat<(v4i8 (sub (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
315 def: Pat<(v4i8 (select I1:$Pu, V4I8:$Rs, V4I8:$Rt)),
317 def: Pat<(v2i16 (select I1:$Pu, V2I16:$Rs, V2I16:$Rt)),
323 def: Pat<(v8i8 (vselect V8I1:$Pu, V8I8:$Rs, V8I8:$Rt)),
325 def: Pat<(v4i16 (vselect V4I1:$Pu, V4I16:$Rs, V4I16:$Rt)),
327 def: Pat<(v2i32 (vselect V2I1:$Pu, V2I32:$Rs, V2I32:$Rt)),
333 def: Pat<(i1 (seteq V4I8:$Rs, V4I8:$Rt)),
335 def: Pat<(i1 (setgt V4I8:$Rs, V4I8:$Rt)),
337 def: Pat<(i1 (setugt V4I8:$Rs, V4I8:$Rt)),
340 def: Pat<(i1 (seteq V2I16:$Rs, V2I16:$Rt)),
342 def: Pat<(i1 (setgt V2I16:$Rs, V2I16:$Rt)),
344 def: Pat<(i1 (setugt V2I16:$Rs, V2I16:$Rt)),
350 : Pat<(CmpTy (CmpOp Value:$Rs, Value:$Rt)),
371 def: Pat<(v2i1 (setne V2I32:$Rs, V2I32:$Rt)),
377 def: Pat<(v4i8 (trunc V4I16:$Rs)),
388 def: Pat<(v2i16 (trunc V2I32:$Rs)),
395 def: Pat<(i64 (HexagonVSXTBH I32:$Rs)), (S2_vsxtbh I32:$Rs)>;
396 def: Pat<(i64 (HexagonVSXTBW I32:$Rs)), (S2_vsxthw I32:$Rs)>;
398 def: Pat<(v4i16 (zext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>;
399 def: Pat<(v2i32 (zext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
400 def: Pat<(v4i16 (anyext V4I8:$Rs)), (S2_vzxtbh V4I8:$Rs)>;
401 def: Pat<(v2i32 (anyext V2I16:$Rs)), (S2_vzxthw V2I16:$Rs)>;
402 def: Pat<(v4i16 (sext V4I8:$Rs)), (S2_vsxtbh V4I8:$Rs)>;
403 def: Pat<(v2i32 (sext V2I16:$Rs)), (S2_vsxthw V2I16:$Rs)>;
406 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)),
410 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
427 def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)),
432 def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)),
441 def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)),
445 def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)),
449 def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)),
454 def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)),
475 : Pat<(i64 (Op DoubleRegs:$src1, DoubleRegs:$src2)),
501 def: Pat<(truncstorev2i16 V2I32:$Rs, I32:$Rt),
505 def: Pat<(truncstorev4i8 V4I16:$Rs, I32:$Rt),
516 def: Pat<(v2i16 (zextloadv2i8 I32:$Rs)),
519 def: Pat<(v2i16 (sextloadv2i8 I32:$Rs)),
522 def: Pat<(v2i32 (zextloadv2i8 I32:$Rs)),
525 def: Pat<(v2i32 (sextloadv2i8 I32:$Rs)),