Lines Matching refs:IntRegs
163 def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)),
164 (V6_vS32b_ai IntRegs:$addr, 0,
169 def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
171 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
174 def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)),
175 (V6_vS32b_ai_128B IntRegs:$addr, 0,
180 def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
182 (v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)),
188 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>,
190 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
191 (!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>,
216 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
217 (MI VecDblRegs:$src1, IntRegs:$src2)>,
220 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2),
221 (!cast<InstHexagon>(MI#"_128B")VecDblRegs128B:$src1, IntRegs:$src2)>,
226 def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
227 (MI VectorRegs:$src1, IntRegs:$src2)>,
230 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2),
231 (!cast<InstHexagon>(MI#"_128B")VectorRegs128B:$src1, IntRegs:$src2)>,
272 def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
273 (MI VecPredRegs:$src1, IntRegs:$src2)>,
277 IntRegs:$src2),
279 IntRegs:$src2)>,
296 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
297 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
302 IntRegs:$src3),
305 IntRegs:$src3)>,
310 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
311 (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
316 IntRegs:$src3),
319 IntRegs:$src3)>,
324 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
325 (MI VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
330 IntRegs:$src3),
333 IntRegs:$src3)>,
338 def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
339 (MI VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
344 IntRegs:$src3),
347 IntRegs:$src3)>,
394 def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
395 (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>,
400 IntRegs:$src3),
403 IntRegs:$src3)>,
409 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
410 (MI VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
415 IntRegs:$src3),
418 IntRegs:$src3)>,
435 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3),
436 (MI VecDblRegs:$src1, IntRegs:$src2, imm:$src3)>,
440 IntRegs:$src2, imm:$src3),
442 IntRegs:$src2, imm:$src3)>,
447 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4),
448 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4)>,
453 IntRegs:$src3, imm:$src4),
456 IntRegs:$src3, imm:$src4)>,
462 IntRegs:$src4),
464 IntRegs:$src4)>,
470 IntRegs:$src4),
474 IntRegs:$src4)>,
480 IntRegs:$src4),
482 IntRegs:$src4)>,
488 IntRegs:$src4),
492 IntRegs:$src4)>,