Lines Matching refs:Pat
63 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
67 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
71 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
76 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
82 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
87 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
92 def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))),
97 def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))),
102 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
107 def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
112 def : Pat <(v64i8 (bitconvert (v512i1 VecPredRegs:$src1))),
117 def : Pat <(v8i64 (bitconvert (v512i1 VecPredRegs:$src1))),
122 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
127 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
132 def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))),
137 def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))),
142 def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
147 def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
152 def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
157 def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
163 def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)),
169 def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
174 def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)),
180 def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
188 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>,
190 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
196 def: Pat<(IntID VectorRegs:$src1),
200 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1),
206 def: Pat<(IntID VecPredRegs:$src1),
210 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1),
216 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
220 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2),
226 def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
230 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2),
236 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2),
240 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
248 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2),
252 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
260 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2),
264 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
272 def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
276 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
284 def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2),
288 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
296 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
300 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
310 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
314 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
324 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
328 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
338 def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
342 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
352 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
356 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
366 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
370 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
380 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
384 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
394 def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
398 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
409 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
413 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
423 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3),
427 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
435 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3),
439 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
447 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4),
451 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
461 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
467 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
479 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
485 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
830 def: Pat<(v64i16 (trunc v64i32:$Vdd)),