Lines Matching refs:Rd

95   (outs IntRegs:$Rd),
97   "if (p0.new) $Rd = #0"> {
98     bits<4> Rd;
102     let Inst{3-0} = Rd;
108   (outs IntRegs:$Rd),
110   "$Rd = memuh($Rs + #$u3_1)"> {
111     bits<4> Rd;
116     let Inst{3-0} = Rd;
150   (outs IntRegs:$Rd),
152   "$Rd = memub($Rs + #$u4_0)"> {
153     bits<4> Rd;
158     let Inst{3-0} = Rd;
166   (outs IntRegs:$Rd),
168   "$Rd = memw($Rs + #$u4_2)"> {
169     bits<4> Rd;
174     let Inst{3-0} = Rd;
305   (outs IntRegs:$Rd),
307   "$Rd = memh($Rs + #$u3_1)"> {
308     bits<4> Rd;
313     let Inst{3-0} = Rd;
337   (outs IntRegs:$Rd),
339   "$Rd = #-1"> {
340     bits<4> Rd;
344     let Inst{3-0} = Rd;
350   (outs IntRegs:$Rd),
352   "$Rd = sxth($Rs)"> {
353     bits<4> Rd;
357     let Inst{3-0} = Rd;
396   (outs IntRegs:$Rd),
398   "$Rd = sxtb($Rs)"> {
399     bits<4> Rd;
403     let Inst{3-0} = Rd;
411   (outs IntRegs:$Rd),
413   "if (!p0) $Rd = #0"> {
414     bits<4> Rd;
418     let Inst{3-0} = Rd;
424   (outs IntRegs:$Rd),
426   "$Rd = memb($Rs + #$u3_0)"> {
427     bits<4> Rd;
432     let Inst{3-0} = Rd;
440   (outs IntRegs:$Rd),
442   "$Rd = $Rs"> {
443     bits<4> Rd;
447     let Inst{3-0} = Rd;
468   (outs IntRegs:$Rd),
470   "$Rd = and($Rs, #1)"> {
471     bits<4> Rd;
475     let Inst{3-0} = Rd;
496   (outs IntRegs:$Rd),
498   "$Rd = add($Rs, #1)"> {
499     bits<4> Rd;
503     let Inst{3-0} = Rd;
549   (outs IntRegs:$Rd),
551   "if (p0) $Rd = #0"> {
552     bits<4> Rd;
556     let Inst{3-0} = Rd;
572   (outs IntRegs:$Rd),
574   "$Rd = add($Rs,#-1)"> {
575     bits<4> Rd;
579     let Inst{3-0} = Rd;
586   (outs IntRegs:$Rd),
588   "$Rd = #$u6"> {
589     bits<4> Rd;
593     let Inst{3-0} = Rd;
611   (outs IntRegs:$Rd),
613   "if (!p0.new) $Rd = #0"> {
614     bits<4> Rd;
618     let Inst{3-0} = Rd;
640   (outs IntRegs:$Rd),
642   "$Rd = and($Rs, #255)"> {
643     bits<4> Rd;
647     let Inst{3-0} = Rd;
654   (outs IntRegs:$Rd),
656   "$Rd = add(r29, #$u6_2)"> {
657     bits<4> Rd;
661     let Inst{3-0} = Rd;
668   (outs IntRegs:$Rd),
670   "$Rd = memw(r29 + #$u5_2)"> {
671     bits<4> Rd;
675     let Inst{3-0} = Rd;
718   (outs IntRegs:$Rd),
720   "$Rd = zxth($Rs)"> {
721     bits<4> Rd;
725     let Inst{3-0} = Rd;