621              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
624               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
630              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
634               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
744     .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());  in splitExt()
784       .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
809         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
812         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
815         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
821         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
832         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)  in splitShift()
843       .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));  in splitShift()
855         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
858         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);  in splitShift()
861         .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))  in splitShift()
919       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
920       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);  in splitAslOr()
926       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
927       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)  in splitAslOr()
931       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)  in splitAslOr()
948       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
959       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()