672   MachineOperand &Op1 = MI->getOperand(1);  in splitImmediate()  local
673   assert(Op0.isReg() && Op1.isImm());  in splitImmediate()
674   uint64_t V = Op1.getImm();  in splitImmediate()
700   MachineOperand &Op1 = MI->getOperand(1);  in splitCombine()  local
710   if (Op1.isImm()) {  in splitCombine()
712       .addImm(Op1.getImm());  in splitCombine()
713   } else if (Op1.isReg()) {  in splitCombine()
715       .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());  in splitCombine()
733   MachineOperand &Op1 = MI->getOperand(1);  in splitExt()  local
734   assert(Op0.isReg() && Op1.isReg());  in splitExt()
741   unsigned RS = getRegState(Op1);  in splitExt()
744     .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());  in splitExt()
746     .addReg(Op1.getReg(), RS, Op1.getSubReg())  in splitExt()
754   MachineOperand &Op1 = MI->getOperand(1);  in splitShift()  local
756   assert(Op0.isReg() && Op1.isReg() && Op2.isImm());  in splitShift()
775   unsigned RS = getRegState(Op1);  in splitShift()
784       .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
786       .addReg(Op1.getReg(), RS, HiSR);  in splitShift()
809         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
812         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
815         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
821         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
827         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
832         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)  in splitShift()
837         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
843       .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));  in splitShift()
849         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
855         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
858         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);  in splitShift()
861         .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))  in splitShift()
866         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
878   MachineOperand &Op1 = MI->getOperand(1);  in splitAslOr()  local
881   assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());  in splitAslOr()
895   unsigned RS1 = getRegState(Op1);  in splitAslOr()
919       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
922       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
926       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
936       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
948       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
950       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
959       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
961       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()