250         if (&MO == &Op || !MO.isReg() || MO.getSubReg())  in partitionRegisters()
319         if (!Op.getSubReg())  in profit()
323       if (MI->getOperand(1).getSubReg() != 0)  in profit()
411             if (Op.getSubReg())  in isProfitable()
574     unsigned SR = Op.getSubReg();  in createHalfInstr()
621              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
624               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
630              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
634               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
646     assert(!UpdOp.getSubReg() && "Def operand with subreg");  in splitMemRef()
715       .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());  in splitCombine()
724       .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());  in splitCombine()
744     .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());  in splitExt()
746     .addReg(Op1.getReg(), RS, Op1.getSubReg())  in splitExt()
1054     if (!Op.isReg() || !Op.isUse() || !Op.getSubReg())  in replaceSubregUses()
1061     switch (Op.getSubReg()) {  in replaceSubregUses()
1085     if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg())  in collapseRegPairs()