Lines Matching refs:isReg
113 assert(R.isReg()); in getRegState()
169 if (MI->getOperand(1).isReg()) in isFixedInstr()
174 if (MI->getOperand(0).isReg()) in isFixedInstr()
201 if (!Op.isReg()) in isFixedInstr()
250 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
410 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
467 assert(Cond[1].isReg() && "Unexpected Cond vector from AnalyzeBranch"); in collectIndRegsForLoop()
568 if (!Op.isReg()) { in createHalfInstr()
673 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
702 assert(Op0.isReg()); in splitCombine()
713 } else if (Op1.isReg()) { in splitCombine()
722 } else if (Op2.isReg()) { in splitCombine()
734 assert(Op0.isReg() && Op1.isReg()); in splitExt()
756 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift()
881 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
1054 if (!Op.isReg() || !Op.isUse() || !Op.getSubReg()) in replaceSubregUses()
1080 if (!Op.isReg() || !Op.isUse()) in collapseRegPairs()